Barrier Properties of Very Thin Ta and TaN Layers Against Copper Diffusion

Abstract

Diffusion barrier properties of very thin sputtered Ta and reactively sputtered TaN films used as a barrier layer between Cu and Si substrates were investigated using electrical measurement and materials analysis. The Cu/Ta/pt-n junction diodes with the Ta barrier of 5, 10, and 25 nm thicknesses were able to sustain a 30 mm thermal annealing at temperatures up to 450, 500, and 550°C, respectively, without causing degradation to the device's electrical characteristics. The harrier capability of Ta layer can be effectively improved by incorporation of nitrogen in the Ta film using reactive sputtering technique. For the Cu/TaN/pt-n junction diodes with the TaN barrier of 5, 10, and 25 nm thicknesses, thermal stability was able to reach 500, 600, and 700°C, respectively. We found that failure of the very thin Ta and TaN barriers was not related to Ta silicidation at the barrier/Si interface. Failure of the barrier layer is presumably due to Cu diffusion through the barrier layer during the process of thermal annealing via local defects, such as grain boundaries and stress-induced weak points.

Characterization of Sputtered Ta and TaN Films by Spectroscopic Ellipsometry

“…Ta and TaN thin films routinely serve as barriers against copper diffusion in metallization systems of current ultra-large scale integrated (ULSI) circuits [1,2]. For interconnects of the future technology nodes, barrier films of far below 10 nm thickness are required [3].…”

Electrodeposition from a Liquid Cationic Cuprous Organic Complex for Seed Layer Deposition

“…In state-of-the-art wafer technology, a barrier layer of Ta/TaN prevents the diffusion of copper into silicon. [6][7][8] Presently, the copper layer is fabricated via a two-step process. First, a copper seed layer is grown by Physical Vapor Deposition (PVD) and this layer protects the underlying tantalum against oxidation.…”

Modeling the effect of barrier thickness and low-k dielectric on circuit reliability using 3D model

“…However, the high diffusivity of Cu in Si and SiO 2 demands a diffusion barrier layer around the Cu interconnect to prevent Cu out-diffusion and enhancing the circuit reliability [2]. Common material for barrier layer is Ta [3]. As the device feature size goes to 0.18 lm and below, thick barrier layer is found to be undesirable in the circuit application as the total interconnect resistance will be higher [4].…”