Bandpass delta-sigma modulator with 800 MHz center frequency

Jayaraman, A.; Asbeck, P.M.; Nary, K.R.; Beccue, S.; Wang, Keh-Chung

doi:10.1109/gaas.1997.628246

Cited by 28 publications

(11 citation statements)

References 7 publications

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“…Finally, in receiver applications, down conversion stages are eliminated. Recently two bandpass delta-sigma modulators were reported with a 60 MHz center frequency [21] and an 800 MHz center frequency [22]. Both of these sample at 4 GHz.…”

Section: High-performance Adc Architecturesmentioning

confidence: 99%

See 1 more Smart Citation

Analog-to-digital converter survey and analysis

Walden

1999

IEEE J. Select. Areas Commun.

1,808

959

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Abstract-Analog-to-digital converters (ADC's) are ubiquitous, critical components of software radio and other signal processing systems. This paper surveys the state-of-the-art of ADC's, including experimental converters and commercially available parts. The distribution of resolution versus sampling rate provides insight into ADC performance limitations. At sampling rates below 2 million samples per second (Ms/s), resolution appears to be limited by thermal noise. At sampling rates ranging from 2 Ms/s to 4 giga samples per second (Gs/s), resolution falls off by 1 bit for every doubling of the sampling rate. This behavior may be attributed to uncertainty in the sampling instant due to aperture jitter. For ADC's operating at multi-Gs/s rates, the speed of the device technology is also a limiting factor due to comparator ambiguity. Many ADC architectures and integrated circuit technologies have been proposed and implemented to push back these limits. The recent trend toward single-chip ADC's brings lower power dissipation. However, technological progress as measured by the product of the ADC resolution (bits) times the sampling rate is slow. Average improvement is only 1.5 bits for any given sampling frequency over the last six-eight years.Index Terms-Analog-to-digital converters, aperture jitter, comparator ambiguity, input-referred noise, signal-to-noise ratio, spurious-free dynamic range.

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Section: High-performance Adc Architecturesmentioning

confidence: 99%

“…This converter technology has GHz and GHz. Delta-sigma modulators may be designed with a bandpass characteristic [20]- [22]. This is useful when a relatively narrow band of intermediate frequencies contains the signal to be digitized.…”

Section: High-performance Adc Architecturesmentioning

confidence: 99%

Analog-to-digital converter survey and analysis

Walden

1999

IEEE J. Select. Areas Commun.

1,808

959

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“…Table 1-1 summarizes the performance of some of the best state-of-the-art high-speed ADCs. tered at 1GHz AlInAs/GaInAs CT 75.8dB (12) 3.2W 4GHz 1MHz/60MHz EAM [2] in 1MHz centered at band 180MHz 39dB (6) in 60MHz band GaAs CT XAM [12] 41dB (7) in 1.8W 3.2GHz 25MHz/ 25MHz band 100kHz band 66d B (11) in centered at 100kHz band 800MHz CMOS DT XAM [11] 87dB (14) 150mW 64MHz 2MHz…”

Section: State-of-the-art High Speed Adcsmentioning

confidence: 99%

Radio frequency digital-to-analog converter

Luschas¹,

Schreier

Lee

2004

IEEE J. Solid-State Circuits

114

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Dynamic performance of high speed, high resolution digital-to-analog converters (DACs) is limited by distortion at the data switching instants. Inter-symbol interference (ISI), imperfect timing synchronization and clock jitter are all culprits. A DAC output current controlled by an oscillating waveform is proposed to mitigate the effects of the switching distortion. The oscillating waveform should be a multiple (k*fs) of the sampling frequency (fs), where k>1. The waveforms can be aligned so that the data switching occurs in the zero regions of the oscillating output. This makes the DAC insensitive to switch dynamics and jitter. The architecture has the additional benefit of mixing the DAC impulse response energy to a higher frequency. An image of a low IF input signal can therefore be output directly at a high IF or RF frequency for transmit communications applications. A narrowband sigma-delta DAC with eight unit elements is chosen to demonstrate the radio frequency digital-to-analog converter (RF DAC) concept. A sigma-delta architecture allows the current source transistors to be smaller since mismatch shaping is employed. Smaller current source transistors have a lower drain capacitance, allowing large high frequency output impedance to be achieved without an extra cascode transistor. Elimination of the cascode reduces transistor headroom requirements and allows the DAC to be built with a 1.8V supply. The RF DAC prototype is targeted to GSM transmit specifications and implemented in 0.1 8ptm CMOS technology. Measured single-tone SFDR is -75dBc, SNR is 52dB, and IMD3 is -70.8dBc over a 17.5MHz bandwidth centered at 942.5MHz. Measured SNR has the predicted dependence on the phase alignment of the data clock and oscillating pulse.

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“…To perform high IF sampling, quantizer in DR converter requires higher sample rate than the IF being sampled. Several published single-bit CT DR modulators are able to digitize signals from 800 MHz to 1 GHz [3][4][5]. These DR modulators are mainly designed in HBT technologies and can reach SNR of about 60 dB.…”

Section: Introductionmentioning

confidence: 99%

Design of a high-speed CMOS multi-bit quantizer for continuous-time Delta-Sigma Modulator applications

Mariano

Goumballa

Dallet

et al. 2008

Analog Integr Circ Sig Process

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Digital front-end receivers realize direct conversion of an analog signal to digital form at intermediate frequencies (IF), simplifying the overall system design and alleviating the problems associated with IF mixers. The trend is to eliminate any RF/analog mixers and digitize the RF signal as near as possible to the antenna. In order to digitize directly the analog input signal, a high dynamic-range and high-speed ADC is needed. Continuous-Time Bandpass Delta-Sigma Modulator can meet these requirements, using high-performance multi-bit quantizers. This article presents the design of a high-speed CMOS Analog-to-Digital Converter (ADC) which can be used as a quantizer in Continuous-Time Delta-Sigma Modulator. It is designed in a 130 nm CMOS technology from STMicroelectronics. The main features of the ADC are 3-bit resolution with 4 GHz sampling rate in a 0.8-2 GHz bandwidth.

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Bandpass delta-sigma modulator with 800 MHz center frequency

Cited by 28 publications

References 7 publications

Analog-to-digital converter survey and analysis

Analog-to-digital converter survey and analysis

Radio frequency digital-to-analog converter

Design of a high-speed CMOS multi-bit quantizer for continuous-time Delta-Sigma Modulator applications

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