Balun LNA Thermal Noise Analysis and Balancing With Common-Source Degeneration Resistor

Abubaker, Qusai Mohammad; Albasha, Lutfi

doi:10.1109/access.2020.2984314

Cited by 9 publications

(5 citation statements)

References 16 publications

(22 reference statements)

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“…Figure 2 shows the Low Noise Amplifier circuit. It is based on the Balun topology that converts the single-ended input signal into a differential and uses a common gate stage (CG) (M1) and a common source stage (CS) (M2) [14]. The input impedance of this circuit is controlled by M1 transconductance (𝑔𝑔 𝑚𝑚1 ).…”

Section: Receiver Architecturementioning

confidence: 99%

Analysis of Device Mismatches Effect on the Performance of UWB Receiver Front-End in Wireless Body Area Network Sensor Nodes

Kareem

Benali

Trabelsi

2023

Int. J. Interact. Mob. Technol.

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Today it is important to manufacture high quality integrated circuits which are insensitive to device mismatches. This paper presents an analysis of MOSFET transistors mismatches effect on the performance of UWB receiver front-end which constitute the most important part of Wireless Body Area Network sensor node. The receiver is based on Balun LNA with 25% fully differential double-balanced passive mixer. A PMOS and NMOS transistors mismatch models were proposed to determine LNA output offset voltage and mixer offset current respectively. The analysis result suggests that, to minimize NMOS current mismatch, and thus reducing second-order inter modulation distortion, the overdrive voltage must be maximized. A Monte Carlo and harmonic balance simulations were performed using 0.18µm CMOS process to evaluate the impact of mismatch as well as Vth mismatch on the receiver gain and IIP2. Simulation results show that IIP2 of the receiver is less sensitive to mixer NMOS mismatch but receiver gain is more sensitive. The receiver IIP2 confidence interval in case of NMOS mismatch is [24.674, 24.77]dBm and in case of NMOS Vth mismatch is [24.659, 24.857]dBm. This show the robustness of the proposed UWB receiver front end. Therefore the proposed circuit meets the requirement of UWB system perfectly which make it suitable for WBAN applications.

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Section: Receiver Architecturementioning

confidence: 99%

Analysis of Device Mismatches Effect on the Performance of UWB Receiver Front-End in Wireless Body Area Network Sensor Nodes

Kareem

Benali

Trabelsi

2023

Int. J. Interact. Mob. Technol.

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“…Furthermore, new cascode topologies like recycling FCA have been studied and compared. An FCA and recycling FCA was found to be beneficial for high-frequency application due to higher gain-bandwidth product, but due to less transistor count and complexity, the conventional folded cascode amplifier is selected for the first stage [17] [18] .A common source circuit is selected as the output stage due to high input impedance, moderate voltage gain, low output impedance and good output swing [21]. A common gate topology is considerable due to its good gain, but above-mentioned qualities for an amplifier are not satisfied by the topology [22].…”

Section: IImentioning

confidence: 99%

Design and Simulation of Two Stage Wideband CMOS Amplifier in 90 NM Technology

Kunju

Hameed³

2023

IJRITCC

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Design and simulation of 7 GHz CMOS wideband amplifier(CMOSWA) using a modified cascode circuit realized in 90-nm CMOS technology is presented here. The proposed system consists of two stages, namely a modified folded cascode and an inductively degenerated common source amplifier. The circuit is experimented with and without a feedback network. This work discusses the performance variation as a function of reactive components, and the initial stage results in 22 dB gain,2.6 GHz bandwidth, and 40GHz unity gain-bandwidth. The circuit without the feedback network exhibits 30.7dB gain,4.8GHz bandwidth(BW), and 10GHz unity-gain bandwidth(UGB). The reactive feedback network's inclusion helped to achieve 38.7 dB gain, 6.95GHz BW, 30GHz UGB, and 55o phase margin. The circuit consumes 1.4mW power from a 1.8V power supply. Simulation results of the proposed circuit are comparable and better than the reported wideband designs in the literature. Realization of our proposed circuit would add value to the area of wideband amplifier design.

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“…Besides, the structure includes the single-ended to differential conversion. Although several variants of this circuit exist in the literature [4]- [11], this paper explores the optimization of the classical CG-CS topology (Fig. 1).…”

Section: Introductionmentioning

confidence: 99%

“…Despite its low number of components, optimizing these kinds of LNA present some difficulties that diverse methodologies try to overcome by different strategies ranging from analytical expressions [11] to synthesis algorithms [12] or intermediate approaches [13].…”

Section: Introductionmentioning

confidence: 99%

Design-Window Methodology for Inductorless Noise-Cancelling CMOS LNAs

et al. 2022

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This paper presents an optimization methodology for inductorless noise-cancelling CMOS Low-Noise Amplifiers (LNA), whose performance typically depends on a tight balance in the design of two transistor stages. Due to the different functions of the two parts, noise-cancelling amplifiers become very difficult to analyze in detail by closed-form expressions or straight simulations: each section significantly affects the results of the other. In addition, opposed specifications, such as gain and cut-off frequency, suppose another grade of complexity due to the interplay of the two branches of the circuit. As a solution, the proposed methodology uses a visualization of the design window in 2-dimensional space to optimize the different parameters of the specifications without compromising the others. All specification constraints are represented in a single figure instead of one graph per parameter. Compared with most optimization methods, the design window methodology observes the design span instead of isolated design points that might not guarantee feasibility. Furthermore, as a simulation-driven exploration method, it benefits from complete device models with high-order effects that would be too complex to include in analytical expressions but critical to achieving maximum efficiency. As an example of the method, the paper describes the optimization of the well-known CS-CG noisecancelling LNA in 65-nm standard CMOS technology. Final post-layout simulations report very competitive results with a 3.7-dB noise figure, a 17-dB gain, and a cut-off frequency above 7 GHz.

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Balun LNA Thermal Noise Analysis and Balancing With Common-Source Degeneration Resistor

Cited by 9 publications

References 16 publications

Analysis of Device Mismatches Effect on the Performance of UWB Receiver Front-End in Wireless Body Area Network Sensor Nodes

Analysis of Device Mismatches Effect on the Performance of UWB Receiver Front-End in Wireless Body Area Network Sensor Nodes

Design and Simulation of Two Stage Wideband CMOS Amplifier in 90 NM Technology

Design-Window Methodology for Inductorless Noise-Cancelling CMOS LNAs

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