Balancing reliability, cost, and performance tradeoffs with FreeFault

Abstract

Abstract-Memory errors have been a major source of system failures and fault rates may rise even further as memory continues to scale. This increasing fault rate, especially when combined with advent of integrated on-package memories, may exceed the capabilities of traditional fault tolerance mechanisms or significantly increase their overhead. In this paper, we present FreeFault as a hardware-only, transparent, and nearlyfree resilience mechanism that is implemented entirely within a processor and can tolerate the majority of DRAM faults. FreeFault repurposes portions of the last-level cache for storing retired memory regions and augments a hardware memory scrubber to monitor memory health and aid retirement decisions. Because it relies on existing structures (cache associativity) for retirement/remapping type repair, FreeFault has essentially no hardware overhead. Because it requires a very modest portion of the cache (as small as 8KB) to cover a large fraction of DRAM faults, FreeFault has almost no impact on performance. We explain how FreeFault adds an attractive layer in an overall resilience scheme of highly-reliable and highly-available systems by delaying, and even entirely avoiding, calling upon software to make tradeoff decisions between memory capacity, performance, and reliability.

Review of Memory RAS for Data Centers

“…Several solutions are available for preventing predicted UE from occurring. For example, cache lines were controlled to remove errors by isolating 8 KB capacity or less at the expense of system overhead [85][86][87][88]. However, page offline can remove UEs more than 94% by isolating 4 KB capacity without additional hardware expense [27,89].…”

On-Die Dynamic Remapping Cache: Strong and Independent Protection Against Intermittent Faults

“…FreeFault, RelaxFault: FreeFault [23] remaps a faulty DRAM region to a line in Last-Level Cache (LLC) during operation. After the remapping, it pins the cache line and does not access the faulty DRAM region.…”

“…Cache based remapping ECP [41] Archshield [5] FLOWER/Fame [27] CiDRA [28] FreeFault [23] RelaxFault [24] DEFCAM [42] DRC (Ours) DEFCAM: DEFCAM [42] proposed a dynamic remapping mechanism for caches. It redirects access to a faulty cache set to one of the health sets.…”

“…Recent DRAM standards [17], [22] support Post Package Repair to use spare rows against operational faults. Academic works have proposed remapping faulty DRAM cells using pinned last-level cache entries [23], [24], extra cells within a row [25]- [27], and an embedded cache inside a DRAM [28]. They show significant fault tolerance against increasing bitlevel errors.…”