BAG2: A process-portable framework for generator-based AMS circuit design

Chang, Eric Y.; Han, Jaeduk; Bae, Woorham; Wang, Zhongkai; Narevsky, Nathan; Nikolić, Borivoje; Alon, Elad

doi:10.1109/cicc.2018.8357061

Cited by 96 publications

(34 citation statements)

References 8 publications

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“…Some of these limitations are alleviated by the Europractice program in the case of academic and research institutes, which have access to low cost CAD tools, libraries and manufacturing. In the case of analog IPs for silicon there is not a straightforward solution, although some efforts, such as the Berkeley Analog Generator approach [17], [18] go in the direction to offer open-source analog blocks as well.…”

Section: Discussionmentioning

confidence: 99%

An Academic RISC-V Silicon Implementation Based on Open-Source Components

Abella

Bulla

Cabo

et al. 2020

2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)

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The design presented in this paper, called preDRAC, is a RISC-V general purpose processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The preDRAC processor is the first RISC-V processor designed and fabricated by a Spanish or Mexican academic institution, and will be the basis of future RISC-V designs jointly developed by these institutions. This paper summarizes the design tasks, for FPGA first and for SoC later, from high architectural level descriptions down to RTL and then going through logic synthesis and physical design to get the layout ready for its final tapeout in CMOS 65nm technology.

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Section: Discussionmentioning

confidence: 99%

An Academic RISC-V Silicon Implementation Based on Open-Source Components

Abella

Bulla

Cabo

et al. 2020

2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)

View full text Add to dashboard Cite

show abstract

“…However, in fact, it is hard to say we can do it for the layout design in the near future because there are only a few ways to do it right, however there are billions of ways to do it wrong. That means, to make the automation tool work correctly, a designer should constrain the tools very precisely (Habal & Graeb, 2011;Lin, Chang & Lin, 2009), so they spend most of the design time constraining the tools, which is not very efficient (Chang et al, 2018). That is the main reason why the engineers in this field rarely use such automation tools.…”

Section: Reducing Design Time By Reusing Designmentioning

confidence: 99%

“…7 ). For either way, a good script has to have flexible parameterizations ( Chang et al, 2018 ). So, it is not a matter of which tool we would use.…”

Section: Logic (System Semiconductor)mentioning

confidence: 99%

Today’s computing challenges: opportunities for computer hardware design

Bae

2021

PeerJ Computer Science

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Due to the explosive increase of digital data creation, demand on advancement of computing capability is ever increasing. However, the legacy approaches that we have used for continuous improvement of three elements of computer (process, memory, and interconnect) have started facing their limits, and therefore are not as effective as they used to be and are also expected to reach the end in the near future. Evidently, it is a large challenge for computer hardware industry. However, at the same time it also provides great opportunities for the hardware design industry to develop novel technologies and to take leadership away from incumbents. This paper reviews the technical challenges that today’s computing systems are facing and introduces potential directions for continuous advancement of computing capability, and discusses where computer hardware designers find good opportunities to contribute.

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“…Formulated as a constrained nonlinear optimization problem, automated analog circuit sizing can be solved using well-developed optimization algorithms [2,3] . Furthermore, closing the design loop to synthesize GDSII files can be further taken into consideration [4] , with generator-based tools, such as Berkeley Analog Generator Two (BAG2) [5] , which can generate clean Design Rule Check (DRC), Layout Versus Schematic (LVS) layouts, and post-layout simulation data.…”

Section: Introductionmentioning

confidence: 99%

Building a post-layout simulation performance model with global mapping model fusion technique

Wang

Yin

et al. 2022

Tsinghua Sci. Technol.

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Building a post-layout simulation performance model is essential in closing the loop of analog circuits, but it is a challenging task because of the high-dimensional space and expensive simulation cost. To facilitate efficient modeling, this paper proposes a Global Mapping Model Fusion (GMMF) technique. The key idea of GMMF is to reuse the schematic-level model trained by the Artificial Neural Network (ANN) algorithm, and combine it with few mapping coefficients to build the post-simulation model. Furthermore, as an efficient global optimization algorithm, differential evolution is applied to determine the optimal mapping coefficients with few samples. In GMMF, only a small number of mapping coefficients are unknown, so the number of post-layout samples needed is significantly reduced. To enhance practical utility of the proposed GMMF technique, two specific mapping relations, i.e., linear or weakly no-linear and nonlinear, are carefully considered in this paper. We conduct experiments on two topologies of two-stage operational amplifier and comparator in different commercial processes. All the simulation data for modeling are obtained from a parametric design framework. A more than 5 runtime speedup is achieved over ANN without surrendering any accuracy.

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BAG2: A process-portable framework for generator-based AMS circuit design

Cited by 96 publications

References 8 publications

An Academic RISC-V Silicon Implementation Based on Open-Source Components

An Academic RISC-V Silicon Implementation Based on Open-Source Components

Today’s computing challenges: opportunities for computer hardware design

Building a post-layout simulation performance model with global mapping model fusion technique

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