Backend-of-line reliability improvement options for 28nm node technologies and beyond

Aubel, Oliver; Hennesthal, C.; Hauschildt, M.; Beyer, Armand; Poppe, J.; Talut, G.; Gall, Martin; Hahn, Jens; Boemmels, J.; Nopper, Markus; Seidel, Robert

doi:10.1109/iitc.2011.5940295

Cited by 9 publications

(9 citation statements)

References 3 publications

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“…The solution for this line width effect can be found in several ways: first, by process improvement using a low resistance Cu alloy [5] or by using a CoWP cap layer or interface salicidation that were originally introduced for better EM performances [44,45]. More information on process solutions is given in Section 8 of this work.…”

Section: Metal Width and Space Rulesmentioning

confidence: 99%

Physical, Electrical, and Reliability Considerations for Copper BEOL Layout Design Rules

Shauly

2018

JLPEA

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The continuous scaling needed for better performance and higher density has introduced some new challenges to the back end of line (BEOL) in terms of layout and design. Reductions in metal line width, spacing, and thickness require major changes in both process and design environments. Advanced deep-submicron layout design rules (DRs) should now consider many new proximity effects and reliability concerns due to high electrical fields and currents, planarization-related coverage effects, etc. It is, therefore, necessary to redefine many of the common DRs. For example, space rules now have a complex definition, including both line width and parallel length. In addition, new rules have been introduced to represent the challenges of reliability such as stress-induced voids, time-dependent dielectric breakdowns of intermetal dielectrics, dependency on misalignment, sensitivity to double patterning, etc. This review describes a set of copper (Cu) BEOL layout design rules, as used in technologies featuring lengths ranging from 0.15 µm to 20 nm. The verification of layout rules and sensitivity issues related to them are presented. Reliability-related aspects of some rules, like space, width, and via density, are also discussed with additional design-for-manufacturing layout recommendations.Keywords: back end of line; layout design rules; copper technology; inter-metal dielectric time-dependent dielectric breakdown (IMD-TDDB) M2-M5) have similar or slightly increased thicknesses when compared with the M1 layer, and are mostly used for connections between various devices. Semi-global (M6-M7, 0.35-0.9 µm) and global (M8, 0.9-3.3 µm) lines are used for power buses, transmission lines, and inductors.In order to achieve a tight pitch of M1 and semi-global lines with a high-density design, interconnects are used to connect high-density-logic transistors, standard cells, and other functional blocks in a system on chip (SoC). In general, application-specific integrated circuits (ASICs) and SoCs tend to use a combination of interconnect metals with a large number of MI lines (semi-global) for applications such as highly parallel graphics processing units (GPUs), field-programmable gate arrays (FPGAs), and multi-core smartphone processors (multiple central processing unit (CPU) and GPU cores). In contrast, devices for applications of radio frequency CMOS (RFCMOS), millimeter wave (mmWave), and WiFi use several layers of semi-global and global lines for inductors, transmission lines, and more. From a practical point of view, the set of rules relating to specific types of interconnect do not change based on their use in various applications. This is because many electronic design automation (EDA) tools such as design rule checks (DRCs), BEOL RC modeling, and even dummy fill insertions also need to be adjusted. Instead, the platform process design kit (PDK) includes a large set of metal combinations so that the designer may select one based on their integrated circuit (IC) needs. For example, WiFi ICs, designed using the 65 nm RFCMOS...

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Section: Metal Width and Space Rulesmentioning

confidence: 99%

Physical, Electrical, and Reliability Considerations for Copper BEOL Layout Design Rules

Shauly

2018

JLPEA

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“…Temperature is strongly in uencing the di erent migration mechanisms in metal material. The probability of issues due to thermally activated migration e ects becomes more prominent with ongoing technology development [1]. Areas with increased local temperature su er from higher probability of dislocation than cooler areas.…”

Section: Interaction Of Thermal Effects Thermal Migration and Electrmentioning

confidence: 99%

“…Especially, the placement and routing steps have a high potential of generating EM-robust solutions because they strongly in uence the EM parameters, temperature, interconnect geometry, and current density [3].…”

Section: Towards a Robust Em-aware Designmentioning

confidence: 99%

The need and opportunities of electromigration-aware integrated circuit design

Bigalke

Lienig

Jerke

et al. 2018

Proceedings of the International Conference on Computer-Aided Design

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Electromigration (EM) is becoming a progressively severe reliability challenge due to increased interconnect current densities. A shift from traditional (post-layout) EM veri cation to robust (pro-active) EM-aware design-where the circuit layout is designed with individual EM-robust solutions-is urgently needed. This tutorial will give an overview of EM and its e ects on the reliability of present and future integrated circuits (ICs). We introduce the physical EM process and present its speci c characteristics that can be a ected during physical design. Examples of EM countermeasures which are applied in today's commercial design ows are presented. We show how to improve the EM-robustness of metallization patterns and we also consider mission pro les to obtain application-oriented current-density limits. The increasing interaction of EM with thermal migration is investigated as well. We conclude with a discussion of application examples to shift from the current post-layout EM veri cation towards an EM-aware physical design process. Its methodologies, such as EM-aware routing, increase the EM-robustness of the layout with the overall goal of reducing the negative impact of EM on the circuit's reliability.

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“…Alloying copper with Al or Mn, using self aligned CuSiN, CuGeN, MnSiO were all shown to improve EM lifetime, because of lowered grain boundary or copper/cap diffusion rates. A most significant lifetime enhancement is obtained when metal cap layers are implemented [8][9][10][11][12][13]. At 55nm line width a 100X median lifetime improvement is reported for CoWP.…”

Section: Metal Reliabilitymentioning

confidence: 99%