Back to Thin-Core Massively Parallel Processors

Marowka, Ami

doi:10.1109/mc.2011.133

Cited by 33 publications

(13 citation statements)

References 10 publications

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“…A recent paper in IEEE Computer [63] observes that the widely accepted RAM model for sequential computation is the reason for the huge progress that has occurred in sequential computation over the past 60 years and observes that a single widely acceptable model for parallel computation could result in similar successes in parallel computation. It describes several features that this parallel model and its target architectures should satisfy, including encouraging parallel solutions to applications that are easy to use, energy efficient, scalable, and highly portable.…”

Section: Observations and Consequences Of The Preceding Resultsmentioning

confidence: 99%

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Comparisons of air traffic control implementations on an associative processor with a MIMD and consequences for parallel computing

Yuan¹,

Baker²,

Meilander³

2013

Journal of Parallel and Distributed Computing

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This paper has two complementary focuses. The first is the system design and algorithmic development for air traffic control (ATC) using an associative SIMD processor (AP). The second is the comparison of this implementation with a multiprocessor implementation and the implications of these comparisons. This paper demonstrates how one application, ATC, can more easily, more simply, and more efficiently be implemented on an AP than is generally possible on other types of traditional hardware. The AP implementation of ATC will take advantage of its deterministic hardware to use static scheduling. The software will be dramatically smaller and cheaper to create and maintain. Likewise, a large AP system will be considerably simpler and cheaper than the MIMD hardware currently used. While APs were used for ATC-type applications earlier, these are no longer available. We use a ClearSpeed CSX600 accelerator to emulate the AP solutions of ATC on an ATC prototype consisting of eight data-intensive ATC real-time tasks. Its performance is compared with an 8-core multiprocessor (MP) using OpenMP. Our extensive experiments show that the AP implementation meets all deadlines while the MP will regularly miss a large number of deadlines. The AP code will be similar in size to sequential code for the same tasks and will avoid all of the additional support software needed with an MP to handle dynamic scheduling, load balancing, shared resource management, race conditions, * Corresponding author Email addresses: myuan@cs.kent.edu (Man(Mike) Yuan), jbaker@cs.kent.edu (Johnnie W. Baker), wllcm@att.net (Will C. Meilander) 1 This is the first author footnote. Preprint submitted to Journal of Parallel and Distributed Computing August 15, 2012false sharing, etc. At this point, essentially only MIMD systems are built. Many of the advantages of using an AP to solve an ATC problem would carry over to other applications. AP solutions for a wide variety of applications will be cited in this paper. Applications that involve a high degree of data parallelism such as database management, text processing, image processing, graph processing, bioinformatics, weather modeling, managing UAS (Unmanned Aircraft Systems or drones) etc, are good candidates for AP solutions. This raises the issue of whether we should routinely consider using non-multiprocessor hardware like the AP for applications where substantially simpler software solutions will normally exist. It also raises the question of whether the use of both AP and MIMD hardware in the same system could provide more versatility and efficiency. Either the AP or MIMD could serve as the primary system but could hand off jobs it could not handle efficiently to the other system.

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Section: Observations and Consequences Of The Preceding Resultsmentioning

confidence: 99%

“…The result is that most legacy applications are still waiting to be parallelized. These and related issues are discussed further in [63].…”

Section: Observations and Consequences Of The Preceding Resultsmentioning

confidence: 99%

Comparisons of air traffic control implementations on an associative processor with a MIMD and consequences for parallel computing

Yuan¹,

Baker²,

Meilander³

2013

Journal of Parallel and Distributed Computing

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“…The HAEC Box is the motivating target platform for the design and development of the HAEC-SIM framework. In this architecture, the computing nodes are assumed to consist of 3D stacked processor chips with thousands of 'thin' cores and local memory [19] offering massive intra-node parallelism. The computing node topology is assumed to be 3D with n = 64 nodes organized as 4×4×4.…”

Section: The Haec-sim Framework 31 Motivating Platform Characteristicsmentioning

confidence: 99%

HAEC-SIM: A Simulation Framework for Highly Adaptive Energy-Efficient Computing Platforms

Bielert¹,

Ciorba²,

Feldhoff³

et al. 2015

Proceedings of the Eighth EAI International Conference on Simulation Tools and Techniques

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This work presents a new trace-based parallel discrete event simulation framework designed for predicting the behavior of a novel computing platform running energy-aware parallel applications. Discrete event traces capture the runtime behavior of parallel applications on existing systems and form the basis for the simulation. The simulation framework processes the events of the input trace by applying simulation models that modify event properties. Thus, the output are again event traces that describe the predicted application behavior on the simulated target platform. Both input and simulated traces can be visualized and analyzed with established tools. The modular design of the framework enables the simulation of different aspects such as temporal performance and energy efficiency by applying distinct simulation models e.g.: (i) A performance model for communication that allows to evaluate the target communication topology and link properties. (ii) An energy model for computations that is based on measurements of current hardware. We showcase the potential of this simulation by simulating the execution of benchmark applications to explore design alternatives of highly adaptive and energy-efficient computing applications and platforms.

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“…In this architecture, the compute nodes consist of 3-D stacked processor chips with thousands of 'thin' cores [15] offering massive intranode parallelism. This parallelism is not modeled explicitly in haec sim and is abstracted.…”

Section: Modeling a High Performance-low Energy Computermentioning

confidence: 99%

Analysis of Parallel Applications on a High Performance–Low Energy Computer

Ciorba

Ilsche

Franz

et al. 2014

Lecture Notes in Computer Science

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Abstract. In this paper, we propose a holistic approach for the analysis of parallel applications on a high performance-low energy computer (called the HAEC platform). The HAEC platform is currently under design and refers to an architecture in which multiple 3-D stacked massively parallel processor chips are optically interconnected on a single board and multiple parallel boards are interconnected using short-range high-speed wireless links. Although not exclusively targeting high performance computing (HPC), the HAEC platform aims to deliver high performance at low energy costs, which are essential features for future HPC platforms. At the core of the proposed approach is a trace-driven simulator called haec sim which we developed to simulate the behavior of parallel applications running on this hardware. We investigate several mapping layouts to assign the parallel applications to the HAEC platform. We concentrate on analyzing the communication performance of the HAEC platform running parallel applications. The simulator can employ two communication models: dimension order routing (DOR) and practical network coding (PNC). As a first example of the usefulness of the proposed holistic analysis approach, we present simulation results using these communication models on a communication-intensive parallel benchmark. These results highlight the potential of the mapping strategies and communication models for analyzing the performance of various types of parallel applications on the HAEC platform. This work constitutes the first step towards more complex simulations and analyses of performance and energy scenarios than those presented herein.

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Back to Thin-Core Massively Parallel Processors

Cited by 33 publications

References 10 publications

Comparisons of air traffic control implementations on an associative processor with a MIMD and consequences for parallel computing

Comparisons of air traffic control implementations on an associative processor with a MIMD and consequences for parallel computing

HAEC-SIM: A Simulation Framework for Highly Adaptive Energy-Efficient Computing Platforms

Analysis of Parallel Applications on a High Performance–Low Energy Computer

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