Analysis of Parallel Applications on a High Performance–Low Energy Computer

Abstract

Abstract. In this paper, we propose a holistic approach for the analysis of parallel applications on a high performance-low energy computer (called the HAEC platform). The HAEC platform is currently under design and refers to an architecture in which multiple 3-D stacked massively parallel processor chips are optically interconnected on a single board and multiple parallel boards are interconnected using short-range high-speed wireless links. Although not exclusively targeting high performance computing (HPC), the HAEC platform aims to deliver high performance at low energy costs, which are essential features for future HPC platforms. At the core of the proposed approach is a trace-driven simulator called haec sim which we developed to simulate the behavior of parallel applications running on this hardware. We investigate several mapping layouts to assign the parallel applications to the HAEC platform. We concentrate on analyzing the communication performance of the HAEC platform running parallel applications. The simulator can employ two communication models: dimension order routing (DOR) and practical network coding (PNC). As a first example of the usefulness of the proposed holistic analysis approach, we present simulation results using these communication models on a communication-intensive parallel benchmark. These results highlight the potential of the mapping strategies and communication models for analyzing the performance of various types of parallel applications on the HAEC platform. This work constitutes the first step towards more complex simulations and analyses of performance and energy scenarios than those presented herein.

HAEC-SIM: A Simulation Framework for Highly Adaptive Energy-Efficient Computing Platforms

“…The HAEC Box [9] [7] refers to a new high performance-low energy parallel computing platform. The HAEC Box is the motivating target platform for the design and development of the HAEC-SIM framework.…”

“…The first row indicates the name of the mapping strategy used. The strategies available in HAEC-SIM are: xyz (default), block xyz, and random mapping [7]. The third row denotes the fact that the computing node with coordinates (0,0,0) is allocated two locations, and that these locations have IDs 38 and 72 (in this case denoting the MPI ranks of the application processes).…”

“…As mentioned in Section 3.3.2 modeling the system state is ongoing. We use practical network coding (PNC) [20] [7] as communication model. The PNC model is implemented into HAEC-SIM as the static network model simulation module; the implementation has been successfully verified via the usage of different test cases for which the exact solution is known.…”