Back gate effects on threshold voltage sensitivity to SOI thickness in fully-depleted SOI MOSFETs

Noguchi, M.; Numata, T.; Mitani, Y.; Shino, T.; Kawanaka, S.; Oowaki, Y.; Toriumi, Akira

doi:10.1109/55.892435

Cited by 16 publications

(4 citation statements)

References 10 publications

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“…Where ρot,it(x) is a charge distribution of the radiationinduced oxide-trapped or interface-trapped charge, Cox is the oxide capacitance, and tox is the oxide thickness. According to (3) and ( 4), the positive trapped charge caused by TID effects, accumulates in the BOX film, namely ρot,it(x) > 0, results in a negative shift of Vt in the back-gate, which leads to a similar drift in the front gate through the inter-gate coupling effect [29]. Fig.…”

Section: A the Influence Of The Box Thicknessmentioning

confidence: 99%

Simulation of Total Ionizing Dose (TID) Effects Mitigation Technique for 22 nm Fully-Depleted Silicon-on-Insulator (FDSOI) Transistor

Yan

et al. 2020

IEEE Access

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Based on 22 nm ultrathin-body fully depleted silicon-on-insulator (UTB-FDSOI) transistors, we propose a novel structure of buried insulator layer aiming at total ionizing dose (TID) effects mitigation. Using technology computer-aided design (TCAD) tools, we focus on the influences of UTB-FDSOI devices with different structures and parameters on TID effects, such as buried oxide (BOX) layer thickness, buried Si3N4 layer, and electron traps. First, we construct four types of UTB-FDSOI N-type metal-oxide semiconductor (NMOS) devices numerically, in which the novel device features a buried silicon-oxidenitride-oxide-silicon (SONOS) structure. Then, the transfer characteristics and trapped charge distribution of these devices are studied under different irradiation doses. It is known that a thinner BOX layer could lead to slighter TID effects, and the buried nitride layer and the electron traps could reduce the TID-induced leakage current (Ioff). Employing these optimization structures for TID effects hardness, the innovative transistor shows much better resistance against TID effects compared to the conventional FDSOI transistors. In addition, the threshold voltage of the novel device could be increased by applying appropriate bias conditions, similar to those of programming SONOS memory, so that the Ioff caused by TID irradiation further decreases. These results provide useful guidance for designers to achieve TID effects mitigation of SOI devices.

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Section: A the Influence Of The Box Thicknessmentioning

confidence: 99%

Simulation of Total Ionizing Dose (TID) Effects Mitigation Technique for 22 nm Fully-Depleted Silicon-on-Insulator (FDSOI) Transistor

Yan

et al. 2020

IEEE Access

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“…However, in sub 30 nm channel length regime, Si t needs to be scaled below 5nm; therefore, the large parasitic series resistance and threshold voltage sensitivity to Si t variation become serious issues [1,2]. The extended source and drain offer low source and drain resistance, respectively, and facilitate better source and drain contacts and consequently decrease the total series resistance [3].…”

Section: Introductionmentioning

confidence: 99%

Modeling of Sub Threshold Current and Sub Threshold Swing of Short-Channel Fully-Depleted SOI MOSFET with Back-Gate Control

Dubey¹,

Mishra²

2017

SMSJ

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“…However, in a sub-30-nm channel length regime, t Si needs to be scaled below 5 nm; therefore, the large parasitic series resistance and threshold-voltage sensitivity to t Si variation become serious issues. 3,6,7 The extended source and drain in recessed-source/drain (Re-S/D) SOI MOSFETs offer low source and drain resistance, respectively, and facilitate better source and drain contacts, consequently decreasing the total series resistance. The improved on-current drive capability of the Re-S/D SOI MOSFETs may be attributed to the aforementioned fact.…”

Section: Introductionmentioning

confidence: 99%

An Analytical Threshold Voltage Model of Fully Depleted (FD) Recessed-Source/Drain (Re-S/D) SOI MOSFETs with Back-Gate Control

Saramekala

Tiwari

2016

Journal of Elec Materi

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This paper presents an analytical threshold voltage model for back-gated fully depleted (FD), recessed-source drain silicon-on-insulator metal-oxide-semiconductor field-effect transistors (MOSFETs). Analytical surface potential models have been developed at front and back surfaces of the channel by solving the two-dimensional (2-D) Poisson's equation in the channel region with appropriate boundary conditions assuming a parabolic potential profile in the transverse direction of the channel. The strong inversion criterion is applied to the front surface potential as well as on the back one in order to find two separate threshold voltages for front and back channels of the device, respectively. The device threshold voltage has been assumed to be associated with the surface that offers a lower threshold voltage. The developed model was analyzed extensively for a variety of device geometry parameters like the oxide and silicon channel thicknesses, the thickness of the source/drain extension in the buried oxide, and the applied bias voltages with back-gate control. The proposed model has been validated by comparing the analytical results with numerical simulation data obtained from ATLASä, a 2-D device simulator from SILVACO.

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Back gate effects on threshold voltage sensitivity to SOI thickness in fully-depleted SOI MOSFETs

Cited by 16 publications

References 10 publications

Simulation of Total Ionizing Dose (TID) Effects Mitigation Technique for 22 nm Fully-Depleted Silicon-on-Insulator (FDSOI) Transistor

Simulation of Total Ionizing Dose (TID) Effects Mitigation Technique for 22 nm Fully-Depleted Silicon-on-Insulator (FDSOI) Transistor

Modeling of Sub Threshold Current and Sub Threshold Swing of Short-Channel Fully-Depleted SOI MOSFET with Back-Gate Control

An Analytical Threshold Voltage Model of Fully Depleted (FD) Recessed-Source/Drain (Re-S/D) SOI MOSFETs with Back-Gate Control

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