AVERT: An elaborate model for simulating variable retention time in DRAMs

Kim, Dae-Hyun; Cha, Soonyoung; Milor, Linda

doi:10.1016/j.microrel.2015.06.064

Cited by 3 publications

(1 citation statement)

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“…ror models 4 ⃝ based on a previous understanding of DRAM errors (e.g., from past experiments or scientific studies). Examples of such error models include: analytical models based on understanding DRAM failure modes (e.g., sources of runtime faults [51,60,149,[371][372][373]), parametric statistical models that provide useful summary statistics (e.g., lognormal distribution of cell data-retention times [276,277,[374][375][376][377][378][379][380], exponential distribution of the time-in-state of cells susceptible to variable-retention time (VRT) [65,94,150,166,367,[381][382][383][384][385][386][387][388][389]), physics-based simulation models (e.g., TCAD [232,374,[390][391][392] and SPICE models [14,59,78,106,109,283,[393][394][395]), and empirically-determined curves that predict observations well (e.g., single-bit error rates…”

Section: Testing Modelingmentioning

confidence: 99%

Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

Patel

Kim

Shahroodi

et al. 2020

2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

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Generational improvements to commodity DRAM throughout half a century have long solidified its prevalence as main memory across the computing industry. However, overcoming today's DRAM technology scaling challenges requires new solutions driven by both DRAM producers and consumers. In this paper, we observe that the separation of concerns between producers and consumers specified by industry-wide DRAM standards is becoming a liability to progress in addressing scaling-related concerns.To understand the problem, we study four key directions for overcoming DRAM scaling challenges using system-memory cooperation: (i) improving memory access latencies; (ii) reducing DRAM refresh overheads; (iii) securely defending against the RowHammer vulnerability; and (iv) addressing worsening memory errors. We find that the single most important barrier to advancement in all four cases is the consumer's lack of insight into DRAM reliability. Based on an analysis of DRAM reliability testing, we recommend revising the separation of concerns to incorporate limited information transparency between producers and consumers. Finally, we propose adopting this revision in a two-step plan, starting with immediate information release through crowdsourcing and publication and culminating in widespread modifications to DRAM standards.

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