Autonomous System on a Chip Adaptation through Partial Runtime Reconfiguration

French, Matthew; Anderson, E.; Kang, Dong-In

doi:10.1109/fccm.2008.55

Cited by 15 publications

(10 citation statements)

References 13 publications

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“…Some works used the OPBHWICAP [Gelado et al 2006;Papadimitriou et al 2007;Delahaye et al 2007;Claus et al 2007Claus et al , 2008French et al 2008;Liu et al 2009] whereas a few experimented with the XPSHWICAP [Liu et al 2009]. On the other hand, customized reconfiguration controllers aim to speedup reconfiguration and/or release the processor time to other tasks, such as the reconfiguration management under the supervision of an operating system [Santambrogio et al 2008].…”

Section: Reconfiguration Time and Throughputmentioning

confidence: 99%

“…The measured times mainly concern the phase to pull the bitstream from the offchip memory to the local memory of the processor, copy it from the local memory of the processor to the ICAP, and send it from the ICAP to the FPGA configuration memory [Gelado et al 2006;Papadimitriou et al 2007;French et al 2008]. These subtasks iterate until the entire partial bitstream is written to the configuration memory [Papadimitriou et al 2010].…”

Section: Reconfiguration Time and Throughputmentioning

confidence: 99%

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Performance of partial reconfiguration in FPGA systems

Papadimitriou

Dollas

Hauck

2011

ACM Trans. Reconfigurable Technol. Syst.

109

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Fine-grain reconfigurable devices suffer from the time needed to load the configuration bitstream. Even for small bitstreams in partially reconfigurable FPGAs this time cannot be neglected. In this article we survey the performance of the factors that contribute to the reconfiguration speed. Then, we study an FPGA-based system architecture and with real experiments we produce a cost model of Partial Reconfiguration (PR). This model is introduced to calculate the expected reconfiguration time and throughput. In order to develop a realistic model we take into account all the physical components that participate in the reconfiguration process. We analyze the parameters that affect the generality of the model and the adjustments needed per system for error-free evaluation. We verify it with real measurements, and then we employ it to evaluate existing systems presented in previous publications. The percentage error of the cost model when comparing its results with the actual values of those publications varies from 36% to 63%, whereas existing works report differences up to two orders of magnitude. Present work enables a user to evaluate PR and decide whether it is suitable for a certain application prior entering the complex PR design flow.

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Section: Reconfiguration Time and Throughputmentioning

confidence: 99%

Section: Reconfiguration Time and Throughputmentioning

confidence: 99%

Performance of partial reconfiguration in FPGA systems

Papadimitriou

Dollas

Hauck

2011

ACM Trans. Reconfigurable Technol. Syst.

109

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“…An example of this is the work from Fahmy et al where hardware processing components are made to appear as software components in the run-time system, enabling their inclusion in adaptive applications [6]. Full system autonomy was demonstrated via partial reconfiguration in [7]. Here, the system realizes a significant reduction in size compared to static implementations and an equally impressive reduction in reaction times compared to alternative solutions.…”

Section: Overviewmentioning

confidence: 99%

OpenPR: An Open-Source Partial-Reconfiguration Toolkit for Xilinx FPGAs

Sohanghpurwala

Athanas

Frangieh

et al. 2011

2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and PHD Forum

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The Xilinx Partial Reconfiguration tool kits have been instrumental for performing a wide variety of research on Xilinx FPGAs. These tool kits provide a methodology for creating rectangular partial reconfiguration modules that can be swapped in and out of a static baseline design with one or more PR slots. This thesis presents a new PR toolkit called OpenPR that, for starters, provides similar functionality to the Xilinx PR tool kits. The distinguishing feature of this toolkit is that it is being released as open source, and is intended to be customizable to the needs of researchers. OpenPR has been designed to be easy to use, extensible, portable, and compatible with a wide range of Xilinx software and devices.Aside from supporting the slot-based PR paradigm, OpenPR also provides a solid base for further research into partial reconfiguration and FPGA productivity oriented design tools.

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“…The advantage is more beneficial for applications with a regular structure and abundant parallelism. Thus, FPGA is a promising implementation technology for many areas [3], [8], [10], [12].…”

Section: Introductionmentioning

confidence: 99%

Memory-Efficient IPv4/v6 Lookup on FPGAs Using Distance-Bounded Path Compression

Jiang

Prasanna

2011

2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines

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Abstract-Memory efficiency with compact data structures for Internet Protocol (IP) lookup has recently regained much interest in the research community. In this paper, we revisit the classic trie-based approach for solving the longest prefix matching (LPM) problem used in IP lookup. In particular, we target our solutions for a class of large and sparsely-distributed routing tables, such as those potentially arising in the nextgeneration IPv6 routing protocol. Due to longer prefix lengths and much larger address space, straight-forward implementation of trie-based LPM can significantly increase the number of nodes and/or memory required for IP lookup. Additionally, due to the available on-chip memory and the number of I/O pins of Field Programmable Gate Arrays (FPGAs), state-of-the-art designs cannot support large IPv6 routing tables consisting of over 300K prefixes.We propose two algorithms to compress the uni-bit-trie representation of a given routing table: (1) single-prefix distancebounded path compression and (2) multiple-prefix distancebounded path compression. These algorithms determine the optimal maximum skip distance at each node of the trie to minimize the total memory requirement. Our algorithms demonstrates substantial reduction in the memory footprint compared with the uni-bit-trie algorithm (1.86× for IPv4 and 6.16× for IPv6), and with the original path compression algorithm (1.77× for IPv4 and 1.53× for IPv6). Furthermore, implementation on a state-of-the-art FPGA device shows that our algorithms achieve 466 million lookups per second and are well suited for 100Gbps lookup. This implementation also scales to support larger routing tables and longer prefix length when we go from IPv4 to IPv6.

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Autonomous System on a Chip Adaptation through Partial Runtime Reconfiguration

Cited by 15 publications

References 13 publications

Performance of partial reconfiguration in FPGA systems

Performance of partial reconfiguration in FPGA systems

OpenPR: An Open-Source Partial-Reconfiguration Toolkit for Xilinx FPGAs

Memory-Efficient IPv4/v6 Lookup on FPGAs Using Distance-Bounded Path Compression

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