Performance of partial reconfiguration in FPGA systems

Papadimitriou, Kyprianos; Dollas, Apostolos; Hauck, Scott

doi:10.1145/2068716.2068722

Cited by 109 publications

(57 citation statements)

References 24 publications

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“…The mode configurations are bit-wise very different and when switching between modes many bits need to be changed in the configuration memory. This leads to long reconfiguration times, making RTR less useful for more dynamic applications [8].…”

Section: Brahim Al Farisi Is Sponsored By Iwt Agency For Innovation mentioning

confidence: 99%

A novel tool flow for increased routing configuration similarity in multi-mode circuits

Farisi

Vansteenkiste

Bruneel

et al. 2013

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

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Abstract-A multi-mode circuit implements the functionality of a limited number of circuits, called modes, of which at any given time only one needs to be realised. Using run-time reconfiguration (RTR) of an FPGA, all the modes can be timemultiplexed on the same reconfigurable region, requiring only an area that can contain the biggest mode. Typically, conventional run-time reconfiguration techniques generate a configuration of the reconfigurable region for every mode separately. This results in configurations that are bit-wise very different. Thus, in this case, many bits need to be changed in the configuration memory to switch between modes, leading to long reconfiguration times. In this paper we present a novel tool flow that retains the placement of the conventional RTR flow, but uses TRoute, a reconfigurationaware connection router, to implement the connections of all modes simultaneously. DRoute stimulates the sharing of routing resources between connections of different modes. This results in a significant increase in the similarity between the routing configurations of the modes. In the experimental results it is shown that the number of routing configuration bits that needs to be rewritten is reduced with a factor between 2 and 4 compared to conventional techniques.

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Section: Brahim Al Farisi Is Sponsored By Iwt Agency For Innovation mentioning

confidence: 99%

A novel tool flow for increased routing configuration similarity in multi-mode circuits

Farisi

Vansteenkiste

Bruneel

et al. 2013

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

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“…The Reconfiguration Controller (RC), which oversees this process, is thus a critical component for FPGA fault recovery. A number of investigations have studied general techniques for designing fast, light-weight, and easy-to-use RCs [1]. For space-based FPGA systems in particular, the requirements for resource utilization (area), speed and flexibility should be motivated yet constrained by the desire to reduce the risks of radiation-induced errors to the RC itself.…”

Section: Introductionmentioning

confidence: 99%

A Programmable Configuration Controller for fault-tolerant applications

Gong

Nguyen

et al. 2016

2016 International Conference on Field-Programmable Technology (FPT)

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Abstract-FPGAs are promising candidates for computational tasks in space applications. However, they are susceptible to radiation-induced errors, the most common failure being due to the corruption of their configuration memory. Module-based partial reconfiguration and frame-based scrubbing are the two most commonly used techniques for detecting and recovering from configuration memory errors. Both methods require userdesigned reconfiguration controllers (RC) to read and write FPGA configuration memory data. This paper proposes a Programmable Configuration Controller (PCC) specifically designed for fault-tolerant applications. PCC has a soft Application Specific Instruction Set Processor (ASIP) architecture. The PCC is software programmable using the C language, which allows it to be used in a wide variety of fault-tolerant applications with minimal design and/or hardware overhead. PCC also has instruction extensions to accelerate commonly-used reconfiguration operations such as reading and writing configuration data. Through 5 case studies, we demonstrate that the use of an ASIP architecture for reconfiguration control in applications prone to radiation-induced corruption strikes the right balance between speed, resource utilization and flexibility.

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“…To switch between the different modules during run-time, the complete reconfigurable region is rewritten with the appropriate configuration. Since a whole area needs to be rewritten, this often leads to very long reconfiguration times [2].…”

Section: Introductionmentioning

confidence: 99%

An Automatic Tool Flow for the Combined Implementation of Multi-mode Circuits

Farisi

Bruneel

Cardoso

et al. 2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

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Abstract-A multi-mode circuit implements the functionality of a limited number of circuits, called modes, of which at any given time only one needs to be realised. Using run-time reconfiguration of an FPGA, all the modes can be implemented on the same reconfigurable region, requiring only an area that can contain the biggest mode. Typically, conventional run-time reconfiguration techniques generate a configuration for every mode separately. To switch between modes the complete reconfigurable region is rewritten, which often leads to very long reconfiguration times. In this paper we present a novel, fully automated tool flow that exploits similarities between the modes and uses Dynamic Circuit Specialization to drastically reduce reconfiguration time. Experimental results show that the number of bits that is rewritten in the configuration memory reduces with a factor from 4.6× to 5.1× without significant performance penalties.

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Performance of partial reconfiguration in FPGA systems

Cited by 109 publications

References 24 publications

A novel tool flow for increased routing configuration similarity in multi-mode circuits

A novel tool flow for increased routing configuration similarity in multi-mode circuits

A Programmable Configuration Controller for fault-tolerant applications

An Automatic Tool Flow for the Combined Implementation of Multi-mode Circuits

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