Autonomic fault-handling and refurbishment using throughput-driven assessment

2011 International Conference on Reconfigurable Computing and FPGAs

2011

Self Cite

We employ output-discrepancy consensus to mitigate faulty modules of a Triple Modular Redundant (TMR) arrangement using dynamic partial reconfiguration. Traditionally, the fault-handling resilience of a TMR arrangement is limited to fault(s) in a single TMR instance over the entire mission duration. An additional permanent fault in any of two other TMR instances results in mission's failure. However, in this work, a novel Self-Configuring approach for Discrepancy Resolution (SCDR) is developed and assessed. In SCDR, the occurrence of faults in more than one module initiates the repair mechanism, then upon fault recovery, the system is configured into Concurrent Error Detection (CED) mode. The approach is validated by the complete recovery of a TMR realization of 25 stage Finite Impulse Response (FIR) filter implemented on a reconfigurable platform as a case study. The results show that a self-healing circuit can be realized exploiting the dynamic partial reconfiguration capability of FPGAs while requiring a streamlined operational datapath compared to TMR.

Section: Introductionmentioning

confidence: 99%

A Self-Configuring TMR Scheme Utilizing Discrepancy Resolution

Imran

2011 International Conference on Reconfigurable Computing and FPGAs

2011

Self Cite

“…FPGAs are widely used in space applications, however they are susceptible to transient as well as permanent faults, for example Single Event Upsets (SEUs) in the configuration memory, and Stuck-At (SA) faults in the logic resource [7]. For fault detection capability, a duplex of the design can be instantiated on the chip and a discrepancy in the output can be monitored via a discrepancy detector [8], [9].…”

Section: Introductionmentioning

confidence: 99%

Heterogeneous Concurrent Error Detection (hCED) Based on Output Anticipation

Imran

2011 International Conference on Reconfigurable Computing and FPGAs

2011

Self Cite

A conventional Concurrent Error Detection (CED) technique usually relies on two exact replicas of a given module to provide redundancy in fault-tolerant systems. A discrepancy in one of the two instances flags at least one of them as faulty. We propose a heterogenous redundant FPGA-based system by exploiting the application properties. Consequently, the replicated module is not necessarily an exact copy of the original module but is much less resource and power hungry. In the paper, we discuss two forms of the heterogeneous structure which are spatial and temporal redundancy based. These forms are evaluated using FPGA based hardware implementation of the Discrete Cosine Transform (DCT) block. A necessary condition is derived to declare the DCT block as fault-free. The results show that the heterogeneous spatial redundancy can realize a resource efficient CED pair at the cost of a small latency in error detection. On the other hand, the heterogeneous temporal redundancy can provide permanent faults resource coverage at the cost of reduced throughput with negligible resource overhead.

“…Previous works establish the successful use of Evolutionary Algorithms for adaptive self-recovery of hardware systems based on reconfigurable logic, especially FPGAs [12], [13], [25], [26] and [23]. In [12], a survey of techniques ranging from passive to dynamic in classification are presented to tackle hard faults in SRAM-based FPGAs for small circuit case studies.…”

Section: A Genetic Algorithm-based Refurbishment Of Reconfigurable Hmentioning

confidence: 99%

“…This population could be formed with the single under-refurbishment configuration replicated to form a uniform pool, or with functionally equivalent though physically distinct configurations generated at design-time to form a diverse pool as utilized in [13]. Various techniques can be utilized to form diverse individuals at design time, e.g.…”

Section: Netlist Driven Evolutionary Refurbishment (Nder) Technique Imentioning

confidence: 99%

“…The fitness score needs to be adjusted to have a maximum value of 2 n * m for checking the exit criteria as described later. Alternatively, runtime inputs can also be utilized as proposed in [13] which demonstrates viable and robust performance for self-adaption using evaluation of actual inputs, rather than exhaustive test vectors. This utilizes a confidence interval during which the runtime inputs are monitored based on the premise that not all input combinations need to appear within a given interval.…”

Section: B Marking Of Lutsmentioning

confidence: 99%

See 1 more Smart Citation

Scalable FPGA Refurbishment Using Netlist-Driven Evolutionary Algorithms

Ashraf

2013

IEEE Trans. Comput.

Self Cite

In this work, Field Programmable Gate Array (FPGA) reconfigurability is exploited to realize autonomous fault recovery in mission-critical applications at runtime. The proposed Netlist Driven Evolutionary Refurbishment (NDER) technique utilizes design-time information from the circuit netlist to constrain the search space of the algorithm by up to 98.1% in terms of the chromosome length representing reconfigurable logic elements. This facilitates refurbishment of relatively large-sized FPGA circuits as compared to previous works. Hence, the scalability issue associated with Evolvable Hardware based refurbishment is addressed and improved. Experiments are conducted with multiple circuits from the MCNC benchmark suite to validate the approach and assess its benefits and limitations.Successful refurbishment of the apex4 circuit having a total of 1252 LUTs with 10% spares is achieved in as few as 633 generations on average when subjected to simulated randomly-injected single stuck-at faults. Moreover, the use of design-time information about the circuit undergoing refurbishment is validated as means to increase the tractability of dynamic evolvable hardware techniques.