Automatically Optimizing the Latency, Area, and Accuracy of C Programs for High-Level Synthesis

Abstract

Loops are pervasive in numerical programs, so high-level synthesis (HLS) tools use state-of-the-art scheduling techniques to pipeline them efficiently. Still, the run time performance of the resultant FPGA implementation is limited by data dependences between loop iterations. Some of these dependence constraints can be alleviated by rewriting the program according to arithmetic identities (e.g. associativity and distributivity), memory access reductions, and control flow optimizations (e.g. partial loop unrolling). HLS tools cannot safely enable such rewrites by default because they may impact the accuracy of floating-point computations and increase area usage. In this paper, we introduce the first open-source program optimizer for automatically rewriting a given program to optimize latency while controlling for accuracy and area. Our tool, SOAP3, reports a multi-dimensional Pareto frontier that the programmer can use to resolve the trade-off according to their needs. When applied to a suite of PolyBench and Livermore Loops benchmarks, our tool has generated programs that enjoy up to a 12× speedup, with a simultaneous 7× increase in accuracy, at a cost of up to 4× more LUTs.

Module-per-Object: A Human-Driven Methodology for C++-Based High-Level Synthesis Design

“…Automated source-to-source transformations can result in descriptions that might not exactly match the original code. Gao et al [13] and Cong et al [14] have done similar research.…”

Automated Accelerator Generation and Optimization with Composable, Parallel and Pipeline Architecture

“…In general, performance analysis is mainly performed at either IR level [32,36,28,20,18] or source code level [37]. Since most of the existing work performs analysis without explicitly considering back-end design flow [32,36,18,28,20], their analysis cannot reflect the optimization done by the commercial tool. On the other hand, similar to this paper, [37] builds the performance model with the help of the commercial tool, but [37] provides neither the resource model nor automated code transformation, so users still need to manually change the kernel code while considering the FPGA resource limitation.…”

“…Finally, some frameworks also focus on general-purpose programming languages such as C/C++ [21,35,18]. SOAP3 [18] is a framework that analyzes a kernel at the metasemantic intermediate representation (MIR) graph level and transforms it according to the result of design space exploration. However, SOAP3 adopts regression models for resource estimation, so the model is not general enough to cover nonlinear resource consumption.…”

“…Unlike most existing models [18,20,28,32,36] that analyze the source program directly, many parameters of our proposed model are obtained from the HLS synthesis reports of a few design points. This feature enables our model to capture most scheduling optimizations performed by the HLS tool.…”

“…Analytical Modeling: Fast performance estimation on FP-GAs has become popular in recent years. In general, performance analysis is mainly performed at either IR level [32,36,28,20,18] or source code level [37]. Since most of the existing work performs analysis without explicitly considering back-end design flow [32,36,18,28,20], their analysis cannot reflect the optimization done by the commercial tool.…”