Automated Accelerator Generation and Optimization with Composable, Parallel and Pipeline Architecture

Abstract

CPU-FPGA heterogeneous architectures are attracting ever-increasing attention in an attempt to advance computational capabilities and energy efficiency in today's datacenters. These architectures provide programmers with the ability to reprogram the FPGAs for flexible acceleration of many workloads. Nonetheless, this advantage is often overshadowed by the poor programmability of FPGAs whose programming is conventionally a RTL design practice. Although recent advances in high-level synthesis (HLS) significantly improve the FPGA programmability, it still leaves programmers facing the challenge of identifying the optimal design configuration in a tremendous design space.This paper aims to address this challenge and pave the path from software programs towards high-quality FPGA accelerators. Specifically, we first propose the composable, parallel and pipeline (CPP) microarchitecture as a template of accelerator designs. Such a well-defined template is able to support efficient accelerator designs for a broad class of computation kernels, and more importantly, drastically reduce the design space. Also, we introduce an analytical model to capture the performance and resource trade-offs among different design configurations of the CPP microarchitecture, which lays the foundation for fast design space exploration. On top of the CPP microarchitecture and its analytical model, we develop the AutoAccel framework to make the entire accelerator generation automated. AutoAccel accepts a software program as an input and performs a series of code transformations based on the result of the analytical-model-based design space exploration to construct the desired CPP microarchitecture. Our experiments show that the AutoAccel-generated accelerators outperform their corresponding software implementations by an average of 72x for a broad class of computation kernels.

A CAD-based methodology to optimize HLS code via the roofline model

“…Although several works have been proposed [6,9,[41][42][43]] to automatically explore a large set of FPGA designs, they all assume the initial design to be fully cached or cacheable. For the sake of conciseness, in this Section we only focus on approaches exploring directive-insertion optimizations that, as demonstrated by Siracusa et al [31], are of particular interest in mixed optimization methodologies.…”

SuSy

“…General HLS compilers -Beyond generating systolic arrays, there is also a plethora of work targeting implementing general applications on FPGAs [3,6,16,21,34]. However, experimental results show that there still exists a performance gap between such frameworks and dedicated systolic array compilers like SuSy.…”

HeteroRefactor

“…Figure 1 illustrates our new contributions, highlighted with bold and red, relative to the prior HLS literature. There exists many automated approaches for generating device and host interfaces [20,61,83], exploring parallelization opportunities [24,34,46,83…”

“…The kernels we selected are slightly slower than running on CPU because I6 and I7 in Rosetta are designed to achieve higher energy efficiency but not higher processing throughput compared to CPU [84]. HeteroRefactor aims to reduce resource usage, while prior work [19,24] achieves higher performance than CPU by leveraging more on-chip resources to achieve parallelism. HeteroRefactor could be used jointly with other tools to produce fast and resource-efficient FPGA accelerators.…”

“…and optimizing data movement[10,20,24,46,55,56]. But general methods for reducing resource consumption, pointer support, memory management and recursion support remain as open research questions and no automated kernel refactoring exists yet.…”