Automatic verification of the SCI cache coherence protocol

Stern, Ulrich; Dill, David L.

doi:10.1007/3-540-60385-9_2

Cited by 40 publications

(24 citation statements)

References 11 publications

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“…Most works [4,6,7,9,12,16,18,20,21] concern elaborated protocols using more complex topologies than the fully connected snoop topology of our LNT model. The principal differences to our work are that we focus on a generic interconnect that includes the behavior of all correct implementations and that we study a heterogeneous SoC, rather than verifying a particular coherency protocol for a homogeneous system.…”

Section: Related Workmentioning

confidence: 99%

Formal Analysis of the ACE Specification for Cache Coherent Systems-on-Chip

Kriouile

Serwe

2013

Formal Methods for Industrial Critical Systems

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Abstract. System-on-Chip (SoC) architectures integrate now many different components, such as processors, accelerators, memory, and I/O blocks, some but not all of which may have caches. Because the validation effort with simulation-based validation techniques, as currently used in industry, grows exponentially with the complexity of the SoC, we investigate in this paper the use of formal verification techniques. More precisely, we use the CADP toolbox to develop and validate a generic formal model of an SoC compliant with the recent ACE specification proposed by ARM to implement system-level coherency.

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Section: Related Workmentioning

confidence: 99%

Formal Analysis of the ACE Specification for Cache Coherent Systems-on-Chip

Kriouile

Serwe

2013

Formal Methods for Industrial Critical Systems

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“…Detection of memory bugs also can be performed statically by utilizing explicit model checking [17,33] and program analysis [2,6,8]. As software becomes more complex and diverse, users increasingly rely on run-time bug detection by instrumenting the code with checks, such as in Purify [26], Valgrind [30,31], Intel thread checker [11], DIDUCE [9], Eraser [29], CCured [18], and others [1,4,15,22,23].…”

Section: Related Workmentioning

confidence: 99%

Automatic parallelization of fine-grained meta-functions on a chip multiprocessor

Lee

Tuck

2011

International Symposium on Code Generation and Optimization (CGO 2011)

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Due to the importance of reliability and security, prior studies have proposed inlining meta-functions into applications for detecting bugs and security vulnerabilities. However, because these software techniques add frequent, finegrained instrumentation to programs, they often incur large runtime overheads. In this work, we consider an automatic thread extraction technique for removing these fine-grained checks from a main application and scheduling them on helper threads. In this way, we can leverage the resources available on a CMP to reduce the latency and overhead of fine-grained checking codes.Our parallelization strategy automatically extracts metafunctions from the main application and executes them in customized helper threads -threads constructed to mirror relevant fragments of the main program's behavior in order to keep communication and overhead low. To get good performance, we consider optimizations that reduce communication and balance work among many threads.We evaluate our parallelization strategy on Mudflap, a pointer-use checking tool in GCC. To show the benefits of our technique, we compare it to a manually parallelized version of Mudflap. We run our experiments on an architectural simulator with support for fast queueing operations. On a subset of SPECint 2000, our automatically parallelized code is only 29% slower, on average, than the manually parallelized version on a simulated 8-core system. Furthermore, two applications achieve better speedups using our algorithms than with the manual approach. Also, our approach introduces very little overhead in the main program -it is kept under 100%, which is more than a 5.3× reduction compared to serial Mudflap.

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“…The effectiveness of aggregation is shown by the example we present below: FLASH is the most complex multiprocessor cache coherence protocol that has been formally verified using a theorem-prover. [31], [5], [40], [32], [17], [19]. These methods suffer from the state explosion problem: the number of states for nontrivial numbers of processors and cache lines is very large.…”

Section: Basic Ideamentioning

confidence: 99%

Verification of Cache Coherence Protocols by Aggregation of Distributed Transactions

Park

Dill

1998

Theory of Computing Systems

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Abstract. This paper presents a method to verify the correctness of protocols and distributed algorithms. The method compares a state graph of the implementation with a specification which is a state graph representing the desired abstract behavior. The steps in the specification correspond to atomic transactions, which are not atomic in the implementation.The method relies on an aggregation function, which is a type of abstraction function that aggregates the steps of each transaction in the implementation into a single atomic transaction in the specification. The key idea in defining the aggregation function is that it must complete atomic transactions which have committed but are not finished. This paper illustrates the method on a directory-based cache coherence protocol developed for the Stanford FLASH multiprocessor. The coherence protocol consisting of more than a hundred different kinds of implementation steps has been reduced to a specification with six kinds of atomic transactions. Based on the reduced behavior, it is very easy to prove crucial properties of the protocol including data consistency of cached copies at the user level. This is the first correctness proof verified by a theorem-prover for a cache coherence protocol of this complexity. The aggregation method is also used to prove that the reduced protocol satisfies a desired memory consistency model.

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Automatic verification of the SCI cache coherence protocol

Cited by 40 publications

References 11 publications

Formal Analysis of the ACE Specification for Cache Coherent Systems-on-Chip

Formal Analysis of the ACE Specification for Cache Coherent Systems-on-Chip

Automatic parallelization of fine-grained meta-functions on a chip multiprocessor

Verification of Cache Coherence Protocols by Aggregation of Distributed Transactions

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