Automatic Verification of Sequential Circuits Using Temporal Logic

Abstract

Abstract-Verifying the correctness of sequential circuits has been an important problem for a long time. But lack of any formal and efficient method of verification has prevented the creation of practical design aids for this purpose. Since-all the known techniques of simulation apd prototype testing are time consuming and not very reliable, there is an acute need for such tools. In this paper we describe an automatic verification system for sequential circuits in which specifications are expressed in a propositional temporal logic. In contrast to most other mechanical verification systems, our system does not require any user assistance and is quite;fast-experimental results show that state machines with several hundred states can be checked for correctness in a matter of seconds!The verification system uses a simple and efficient algorithm, called a model checker. The algorithm works in two steps: in the first step, it builds a labeled state-transition graph; and in the second step, it determines the truth of a temporal formula with.respect to the state-transition graph. We discuss two different techniques that we thave implemented for automatically generating the state-transition graphs: The first involves extracting the state graph directly feom the circuit by exhaustive simulation.The second obtains the state graph by compilation from an HDL specification of the original circuit.

Symbolic model checking for sequential circuit verification

“…These methods are frequently based on the use of automatic theorem provers or proof checkers and may require considerable assistance from the user in constructing a correctness proof. In contrast, the most effective techniques for reasoning about sequential behavior usually require a complete exploration of the state space of the circuit [6], [21], [25]. The state exploration techniques are attractive because they are highly automatic: the user simply provides a description of the circuit implementation and its specification; the system does the rest.…”

Formal methods

“…The very first two model checkers were EMC [Clarke and Emerson 1981;Clarke et al 1986;Browne et al 1986] and CAESAR [Queille and Sifakis 1981;Fernandez et al 1996]. SMV [McMillan 1993] is the first model checker to use BDDs.…”

Symmetry and induction in model checking

“…The distinction between model checking and symbolic model checking is pointed out in Figure 1.1. The use of model checking made it possible to nd errors in nontrivial circuits which had been carefully designed [8,27]. With the discovery of symbolic model checking, it is now possible to verify large systems [18,56].…”