Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems

Vasudevan, Shobha; Viswanath, Vinod; Sumners, Rob; Abraham, Jacob A.

doi:10.1109/tc.2007.1073

Cited by 32 publications

(13 citation statements)

References 24 publications

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“…We demonstrate the efficiency of our technique using a non-trivial example. We have in the past constructed the technique to do RTL to RTL combinational equivalence checking at the higher level [25]. Our current work, in principle, can be also be applied to RTL to RTL sequential equivalence checking, since it is effective for source to source checking at the higher level.…”

Section: Discussionmentioning

confidence: 99%

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Sequential equivalence checking between system level and RTL descriptions

Vasudevan

Viswanath

Abraham

et al. 2008

Des Autom Embed Syst

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Sequential equivalence checking between system level descriptions of designs and their Register Transfer Level (RTL) implementations is a very challenging and important problem in the context of Systems on a Chip (SoCs). We propose a technique to alleviate the complexity of the equivalence checking problem, by efficiently decomposing it using compare points. Traditionally, equivalence checking techniques use nominal or functional mapping of latches as compare points. Since we operate at a level where design descriptions are in System Level Languages or Hardware Description Languages, we leverage the information available to us at this level in deducing sequential compare points. Sequential compare points encapsulate the sequential behavior of designs and are obtained by statically analyzing the design descriptions. We decompose the design using sequential compare points and represent the design behavior at these compare points by symbolic expressions. We use a SAT solver to check the equivalence of the symbolic expressions. In order to demonstrate our technique, we present results on a non-trivial case study. We show an equivalence check between a System C description and two different Verilog RTL implementations of a Viterbi decoder, that is a component of the DRM SoC.

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Section: Discussionmentioning

confidence: 99%

“…Hence, there will be 4 observables that correspond to mul_result Every subset of bits assigned, therefore, has a corresponding observable. We call such assignments (to different subsets of bits of the same variable), reassignments, as in [25]. Thus, a reassignment for a variable defines a partition of the bits for the variable.…”

Section: Reassignmentsmentioning

confidence: 99%

Sequential equivalence checking between system level and RTL descriptions

Vasudevan

Viswanath

Abraham

et al. 2008

Des Autom Embed Syst

Self Cite

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“…The success of verification depends on the set of available axioms, rewrite rules, and on the order in which they are applied during the proof process, with no guarantee for a conclusive answer. Similarly, term rewriting techniques, such as [18], are incomplete, as they rely on simple rewriting rules and use non-canonical representations.…”

Section: A Related Workmentioning

confidence: 99%

Function Extraction from Arithmetic Bit-Level Circuits

Ciesielski

Brown

Liu

et al. 2014

2014 IEEE Computer Society Annual Symposium on VLSI

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Abstract-The paper describes a method to derive a polynomial function computed by an arithmetic bit-level circuit. The circuit is modeled as a bit-level network composed of adders and logic gates and computation performed by the circuit is viewed as a flow of binary data through the network. The problem is cast as a Network Flow problem and solved using standard algebraic techniques. Extraction of the arithmetic function from the circuit is accomplished by transforming the expression at the primary outputs into an expression at the primary inputs. Experimental results show application of the method to certain classes of large arithmetic circuits.

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“…The success of verification depends on the set of available axioms, rewrite rules, and on the order in which they are applied during the proof process, with no guarantee for a conclusive answer. Similarly, term rewriting techniques, such as [14], are incomplete, as they rely on simple rewriting rules (distributivity, commutativity, and associativity) and use non-canonical representations.…”

Section: Related Workmentioning

confidence: 99%

Arithmetic Bit-Level Verification Using Network Flow Model

Ciesielski¹,

Brown²,

Rossi

2013

Hardware and Software: Verification and Testing

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Abstract. The paper presents a new approach to functional, bit-level verification of arithmetic circuits. The circuit is modeled as a network of adders and basic Boolean gates, and the computation performed by the circuit is viewed as a flow of binary data through such a network. The verification problem is cast as a Network Flow problem and solved using symbolic term rewriting and simple algebraic techniques. Functional correctness is proved by showing that the symbolic flow computed at the primary inputs is equal to the flow computed at the primary outputs. Experimental results show a potential application of the method to certain classes of arithmetic circuits.

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Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems

Cited by 32 publications

References 24 publications

Sequential equivalence checking between system level and RTL descriptions

Sequential equivalence checking between system level and RTL descriptions

Function Extraction from Arithmetic Bit-Level Circuits

Arithmetic Bit-Level Verification Using Network Flow Model

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