Automatic synthesis and scheduling of multirate DSP algorithms

Abstract

To date, most high-level synthesis systems do not automatically solve present design problems, such as those related to timing associated with the physical implementation of multirate DSP architectures. Whilst others do not trade off area/speed of algorithm efficiently for such architectures. An automatic synthesis methodology based on both retiming techniques together with folding transformations is presented in this paper in order to solve timing problems associated with the implementation of multirate DSP algorithms. We demonstrate that techniques for modeling computational unit latencies, which can influence parameterisations of a multirate DSP IP core, can lead to highly efficient solutions. This is illustrated using a polyphase IIR IDCT example. Using the folding transformation, the control circuit for a hardware sharing multirate DSP is also presented. I IntroductionMultirate digital algorithms are widely used by numerous applications such as speech, audio and video signal coding, fast transforms using filter banks and discrete wavelet analysis of all signal types [1]. A multirate algorithm uses different sample rates within a system, to achieve a computational efficiency that is impossible to obtain within a single-rate system. The key characteristic of multirate algorithms is their high computational efficiency.With the continuous development in SoC technology, the reuse of optimised IP cores has received considerable interest in recent years. New challenges for IP reuse are in locating and characterising the IP core, and efficiently integrating them within SoC designs. Currently, IP cores can be parameterised in terms of aspects such as wordlength size for inputs and outputs, latencies and some other features related to functionality such as the number of taps in the case of a filter. Numerous software and hardware design tools do not fully consider the effects of these parameters (or chip-level engineering issues) on the structure of the derived architecture. Some design issues such as the organisation of the data entering and leaving the various processors, the number of systems employed, levels of pipelining and the handling of numerical truncation can change the characteristics of the complete system, particularly aspect of timing and latency [2,3], and thereby altering the system's function. In order to automatically solve the effects of these issues in multirate DSP systems, a novel methodology is developed in this paper that allows a designer to carry out architectural exploration and synthesis at the algorithm level. This synthesis methodology based on Modular Design Procedure (MDP) [2,3], provides a bridge between the high-level algorithm, architecture mapping techniques and lower level design tools when targeting multirate DSP algorithms.

Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis

“…However conventional techniques usually address various HLS constraints considering uniform-width resources (same word-length for all components and interconnections) [20][21][22][23][24]. This is mainly due to traditional high-level languages used as high-level synthesis input like the C language which only provides computation types with restricted lengths (typically 8/16/ 32/64 data-widths).…”