Automatic Pre-Fetch and Modulo Scheduling Transformations for the Cell BE Architecture

Vujic, Nikola; González, Marc; Martorell, Xavier; Ayguadé, Eduard

doi:10.1007/978-3-540-89740-8_3

Cited by 4 publications

(5 citation statements)

References 12 publications

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“…The V_dir 1 [2], which is mapped by the index_old should be checked first. If it's valid, the dirty bytes in L [4] and L [5] should be written back. Meanwhile, the V_dir 1 [2] is set to be 0.…”

Section: Indalign(index_s) = Oldest(4 5 6 7) (5)mentioning

confidence: 99%

“…Meanwhile, the V_dir 1 [2] is set to be 0. Otherwise, if it's invalid, the V_dir 2 [5] is checked. If it's valid, the dirty data in L [5] is written back.…”

Section: Indalign(index_s) = Oldest(4 5 6 7) (5)mentioning

confidence: 99%

“…Fetching the required short line from the memory, filling the corresponding DE, and setting V_dir 2 [5] to valid. Finally, the node whose data field is 5 moves to the link tail.…”

Section: Indalign(index_s) = Oldest(4 5 6 7) (5)mentioning

confidence: 99%

“…There has been substantial research [1][2][3][4][5][6] on software cache specifically for Cell processor. Eichenberger et al [1] propose a compiler-controlled software cache.…”

Section: Introductionmentioning

confidence: 99%

“…A hybrid access-specific software cache is presented by Marc Gonzalez et al [4,5]. It classifies memory accesses into high locality and irregular, and the corresponding high locality cache and the transactional cache are designed.…”

Section: Introductionmentioning

confidence: 99%

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Adaptive Line Size Cache for Irregular References on Cell Multicore Processor

Cao

Zhao

Chen

et al. 2010

Lecture Notes in Computer Science

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Abstract. Software cache promises to achieve programmability on Cell processor. However, irregular references couldn't achieve a considerable performance improvement since the cache line is always set to a specific size. In this paper, we propose an adaptive cache line prefetching strategy which continuously adjusts cache line size during application execution. Therefore, the transferred data is decreased significantly. Moreover, a corresponding software cacheadaptive line size cache is designed. It introduces a hybrid Tag Entry Arrays, with each mapping to a different line size. It's a hierarchical design in that the misshandler is not invoked immediately when an address is a miss in the short line Tag Entry Array. Instead, the long line Tag Entry Array is checked first, which significantly increases the hit rate. Evaluations indicate that improvement due to the adaptive cache line strategy translates into 3.29 to 5.73 speedups compared to the traditional software cache approach.

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Section: Indalign(index_s) = Oldest(4 5 6 7) (5)mentioning

confidence: 99%

“…Meanwhile, the V_dir 1 [2] is set to be 0. Otherwise, if it's invalid, the V_dir 2 [5] is checked. If it's valid, the dirty data in L [5] is written back.…”

Section: Indalign(index_s) = Oldest(4 5 6 7) (5)mentioning

confidence: 99%

“…Fetching the required short line from the memory, filling the corresponding DE, and setting V_dir 2 [5] to valid. Finally, the node whose data field is 5 moves to the link tail.…”

Section: Indalign(index_s) = Oldest(4 5 6 7) (5)mentioning

confidence: 99%

“…There has been substantial research [1][2][3][4][5][6] on software cache specifically for Cell processor. Eichenberger et al [1] propose a compiler-controlled software cache.…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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