Adaptive and Speculative Memory Consistency Support for Multi-core Architectures with On-Chip Local Memories

Low Power Gated-Clock Design for Multi-core DSP Based SDR Platform

“…G Suh based on the real-time collection of the cache miss rate, dynamically allocated the second-level cache between the different processes to reduce the off-chip memory access [11][12]. N Vujic proposed an adaptive and prediction mechanism for CELL multicore processor code optimized to reduce the execution time of the program [13][14].…”