Automatic parallelization and accelerator offloading for embedded applications on heterogeneous MPSoCs

Aguilar, Miguel Angel; Leupers, Rainer; Ascheid, Gerd; Murillo, Luis Gabriel

doi:10.1145/2897937.2897991

Cited by 22 publications

(10 citation statements)

References 7 publications

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“…Dataflow is used extensively in Digital Signal Processor (DSP) applications and it has proven to be effective in facilitating the exploration of the various stages of parallelism [3]. In addition, the dataflow modeling is commonly used in the design of Multiprocessor Systems-on-Chip (MPSoC) [30]- [1]. The complexity of the video coding standards has increased in the last decades in order to increase the video quality and the user experience.…”

Section: Dataflow Modelingmentioning

confidence: 99%

Multiple Transform Selection Concept Modeling and Implementation Using Dynamic and Parameterized Dataflow Graphs

Haggui¹,

Belghith

Hamidouche

et al. 2022

J Sign Process Syst

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The new video coding standard, Versatile Video Coding (VVC), released by the end of 2020 has increased the coding complexity both at encoder and decoder sides. This complexity increase is due to several coding tools proposed to enhance the coding efficiency. One of these tools is the Multiple Transform Selection (MTS) concept, a new approach for the transform unit. This paper aims at providing a new optimization of the MTS based on dataflow modeling. The proposed approach takes benefit of the different parallelism levels of the MTS in order to create an optimized multicore implementation. Also, this paper study the impact of the dataflow model granularity and the dynamic reconfiguration on the implementation efficiency on x86 multicore architectures. The PREESM tool is used in this study to develop the proposed dataflow models and for the granularity analysis. The dynamic reconfiguration study is here performed using the SPIDER

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Section: Dataflow Modelingmentioning

confidence: 99%

Multiple Transform Selection Concept Modeling and Implementation Using Dynamic and Parameterized Dataflow Graphs

Haggui¹,

Belghith

Hamidouche

et al. 2022

J Sign Process Syst

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“…The dark silicon phenomenon is currently one of the foremost concerns to many researchers. Facing the coexistence of opportunity and challenge, the existing work addresses this problem from different design aspects, such as architecture heterogeneity and application-specific accelerators [17], Onchip Network Designs [18], [19], [20], run-time power and thermal management [21], [22], [23] and variability-aware techniques [13]. Analyzing these methods above, we find that the power and thermal management is the essential solution to address dark silicon phenomenon for on-chip many-core systems.…”

Section: Related Workmentioning

confidence: 99%

Chip Temperature Optimization for Dark Silicon Many-Core Systems

Liu

Yang

et al. 2017

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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In the dark silicon era, a fundamental problem is: given a real-time computation demand, how to determine if an on-chip multiprocessor system is able to accept this demand and to maintain its reliability by keeping every core within a safe temperature range. In this paper, a practical thermal model is described for quick chip temperature prediction. Integrated with the thermal model, we present a Mixed Integer Linear Programming (MILP) model to find the optimal task-to-core assignment with the minimum chip peak temperature. For the worst case where even the minimum chip peak temperature exceeds the safe temperature, a heuristic algorithm, called temperatureconstrained task selection (TCTS), is proposed to optimize the system performance within chip safe temperature. The optimality of the TCTS algorithm is formally proven. Extensive performance evaluations show that our thermal model achieves an average prediction accuracy of 0.0741 • C within 0.2392 ms. The MILP model reduces chip peak temperature of ∼10 • C comparing with traditional techniques. The system performance is increased by 19.8% under safe temperature limitation. Due to the satisfying scalability of our MILP formulation, the chip peak temperature is further decreased by 5.06 • C via the TCTS algorithm. The feasibility of this systematical technique is testified in a real case study as well.

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“…Fundamental properties of real-time systems, such as predictability and observability, remain, of course, as important as ever [5], [6], and harder than ever to guarantee [7], especially with many systems becoming more and more distributed [8]. This shift towards reconfigurable, adaptable systems is an inescapable need to guarantee tomorrow's performance and power consumption [9]: examples include new heterogeneous multi-core adaptable software architectures [10] and application-specific accelerators on reconfigurable hardware (FPGAs) [11]. The vast majority of modern cyber-physical systems are adaptable in some way [12], due to, e.g., market demand for upgrades [13].…”

Section: Introductionmentioning

confidence: 99%

Towards a Programming Paradigm for Reconfigurable Computing: Asynchronous Graph Programming

Garcia¹,

Fryer²

2020

Preprint

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<div>The shift towards reconfigurable systems -hardware</div><div>and software that adapt themselves to an external context-</div><div>promises to unlock unprecedented performance, power consumption, and quality of service. However, reconfiguration imposes several challenges on the design of cyber-physical systems. Current design practices, including software frameworks and programming languages, are ill-prepared for supporting reconfiguration.</div><div>In this paper, we explore Asynchronous Graph Programming, a programming paradigm and an associated model of computation designed for efficient and automated parallelization across processing elements, efficient reconfiguration (i.e., mapping of computational tasks across processing elements), and combining synchronous and asynchronous I/O handling within the same conceptual programming model. We also introduce an analytical model of parallelization, unlocked by Asynchronous Graph Programming, that can inform reconfiguration strategies.</div><div>We analyze the implications of our model through an analysis of reconfiguration scenarios given a program’s characteristics; our analysis quantifies the benefits of reconfiguring software for higher levels of parallelism, given an amount of data left to process. We also introduce Horde, an open source Asynchronous Graph Programming interpreter, and use it to empirically validate the performance advantage of its automatic parallelism capabilities; in our experiments, automatic parallelization from one to four cores improves average case execution time by a factor of 2 and worst case execution time by a factor of 3.</div><div><br></div><div>This manuscript has been accepted at the IEEE International Conference on Emerging Technologies and Factory Automation (ETFA 2020)</div><div><br></div>

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Automatic parallelization and accelerator offloading for embedded applications on heterogeneous MPSoCs

Cited by 22 publications

References 7 publications

Multiple Transform Selection Concept Modeling and Implementation Using Dynamic and Parameterized Dataflow Graphs

Multiple Transform Selection Concept Modeling and Implementation Using Dynamic and Parameterized Dataflow Graphs

Chip Temperature Optimization for Dark Silicon Many-Core Systems

Towards a Programming Paradigm for Reconfigurable Computing: Asynchronous Graph Programming

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