Chip Temperature Optimization for Dark Silicon Many-Core Systems

Abstract

In the dark silicon era, a fundamental problem is: given a real-time computation demand, how to determine if an on-chip multiprocessor system is able to accept this demand and to maintain its reliability by keeping every core within a safe temperature range. In this paper, a practical thermal model is described for quick chip temperature prediction. Integrated with the thermal model, we present a Mixed Integer Linear Programming (MILP) model to find the optimal task-to-core assignment with the minimum chip peak temperature. For the worst case where even the minimum chip peak temperature exceeds the safe temperature, a heuristic algorithm, called temperatureconstrained task selection (TCTS), is proposed to optimize the system performance within chip safe temperature. The optimality of the TCTS algorithm is formally proven. Extensive performance evaluations show that our thermal model achieves an average prediction accuracy of 0.0741 • C within 0.2392 ms. The MILP model reduces chip peak temperature of ∼10 • C comparing with traditional techniques. The system performance is increased by 19.8% under safe temperature limitation. Due to the satisfying scalability of our MILP formulation, the chip peak temperature is further decreased by 5.06 • C via the TCTS algorithm. The feasibility of this systematical technique is testified in a real case study as well.

Contention-Aware Routing for Thermal-Reliable Optical Networks-on-Chip

“…Chip temperature fluctuates temporally and spatially as a result of uneven chip power density and limited heat dissipation techniques. In general, it can vary by up to 30 K across the chip under typical operating conditions [15]. Under these circumstances, the thermal susceptibility of ONoCs has aroused great concern recently [7].…”

“…Vertically on top of the processing layer where the cores are located, ONoCs with 2D-mesh and 2D-torus topologies are employed for inter-processor communication. Considering the DVFS capability of modern processor cores, we assume that each core can operate at four different voltage and frequency levels: 1.250V at 2.4GHz, 1.210V at 2.1GHz, 1.187V at 1.6GHz, and 1.06V at 1.0GHz [15]. Under different operating voltage/frequency levels, we can model the power consumption of processor cores by McPAT v1.0 [31].…”

Dynamic Thermal Management in Many-Core Systems Leveraged by Abstract Modeling

“…Per-core thermal monitoring is the key for DTM development to manage applications entering and leaving the system dynamically. Although recent proposed DTMs [10,13] employ analytical thermal models to predict per-core temperature by profiling the applications at design time, these DTMs prevent thermal monitoring due to the high computational costs and the data-dependency algorithms. Another alternative to avoid thermal monitoring is patterning the many-core to map applications [9].…”

Hybrid Application Mapping for Composable Many-Core Systems: Overview and Future Perspective

“…The dense integration of resources in a many-core chip results in a high density of power consumption on the chip which, in turn, leads to an increased on-chip temperature. Due to their technological limitations, chip packaging and cooling systems often fail to dissipate the generated heat fast enough which may result in overheated regions (so-called hot spots) and even lead to a chip burn-down [74]. To preserve a thermally safe operation, many-core systems employ Dynamic Thermal Management (DTM) schemes which monitor the thermal state of the chip and use mechanisms such as power gating or Dynamic Voltage and Frequency Scaling (DVFS) to prevent or counteract hot spots [75].…”