Automatic modeling of switch-level networks using partial orders (MOS circuits)

Agrawal, P.; Robinson, S.; Szymanski, Thomas G.

doi:10.1109/43.55209

Cited by 14 publications

References 9 publications

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Redundancy removal and test generation for circuits with non-Boolean primitives

Chakradhar¹,

Rotherweiler²,

Agrawal³

1997

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Production VLSI circuits typically consist of primitives like tristate buffers, bidirectional buffers, and bus configurations that assume non-Boolean values like the high-impedance state. We describe a systematic methodology for extending test generation algorithms that work on combinational circuits with only Boolean primitives to full-scan production circuits. Key features of the methodology are illustrated using the energy minimization based test generation algorithm for combinational circuits. The main features of our methodology that make the test generation algorithm practical for large production circuits are: 1) only one Boolean variable is used to represent the value on a signal and all signals assume only Boolean values during the test generation procedure; 2) the function of non-Boolean primitives is separated into Boolean and non-Boolean components with energy functions required only for the Boolean component; and 3) non-Boolean components are implicitly considered in the energy minimization procedure. In this process, no new energy functions other than the normal Boolean gate energy functions are needed. We give a method for identifying and removing redundancies in production circuits using energy minimization. The formulation is also applicable to Boolean satisfiability and BDD methods. We first use the test generation algorithm for identifying undetectable faults and then relax specific constraints in the original test generation problem by ignoring the non-Boolean components. We show that undetectability in the relaxed formulation implies redundancy. We report redundancy removal results for production VLSI circuits, ISCAS 85, and full-scan versions of the ISCAS 89 benchmark circuits.

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Redundancy removal and test generation for circuits with non-Boolean primitives

Chakradhar¹,

Rotherweiler²,

Agrawal³

1997

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Second generation ORCA architecture utilizing 0.5 μm process enhances the speed and usable gate capacity of FPGAs

Britton

Oswald

et al.

Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit

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This paper describes the second generation Optimized Reconfigurable Cell Array (ORCA) FieldProgrammable Gate Arrays (FPGAs). Architectural innovations combined with advanced OSpm process technology result in a family of high capacity and high speed FPGAs. New types of routing resources are included on the FPGA to ensure routing completion. The first ORCA part in the 2C series, the ATT2C15, contains approximately 2.5 million FETs and has a typical logic capability of about 15, OOO usable gates. Preliminary benchmark results confirm the speed and logic capacity of the new parts.

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Automated modeling of custom digital circuits for test

Bose¹

Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition

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Automatic modeling of switch-level networks using partial orders (MOS circuits)

Cited by 14 publications

References 9 publications

Redundancy removal and test generation for circuits with non-Boolean primitives

Redundancy removal and test generation for circuits with non-Boolean primitives

Second generation ORCA architecture utilizing 0.5 μm process enhances the speed and usable gate capacity of FPGAs

Automated modeling of custom digital circuits for test

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