Automatic mapping of system of N-dimensional affine recurrence equations (SARE) onto distributed memory parallel systems

Proceedings of the 2001 ACM/IEEE Conference on Supercomputing

2001

We describe a design methodology which allows a fast design and prototyping of dedicated hardware devices to be used in heterogeneous computations. The platforms used in heterogeneous computations consist of a general-purpose COTS architecture which hosts a dedicated hardware device; parts of the computation are mapped onto the former, parts onto the latter, in a way to improve the overall computation efficiency. We report the design and the prototyping of a FPGA-based hardware board to be used in the search of low-autocorrelation binary sequences. The circuit has been designed by using a recently developed Parallel Hardware Generator (PHG) package which produces a synthesizable VHDL code starting from the specific algorithm expressed as a System of Affine Recurrence Equations (SARE). The performance of the realized devices has been compared to those obtained on the same numerical application on several computational platforms.

Section: Introductionmentioning

confidence: 99%

Parallel dedicated hardware devices for heterogeneous computations

Marongiu¹,

Proceedings of the 2001 ACM/IEEE Conference on Supercomputing

2001

“…The PHG theoretical framework is described in [5,6] while the detailed theory is reported in [7]. The PHG is based on the design flow shown in figure 1.…”

Section: The Phg Packagementioning

confidence: 99%

“…In order to achieve the final circuit description, PHG performs the following steps (figure 1): − parsing of the SARE describing the algorithm through the SIMPLE compiler and generation of the intermediate format; − automatic extraction of parallelism by allocating and scheduling the computations through a processor-time mapping [6,7]. The mapping is represented by an integer unimodular matrix derived through an optimization process [12].…”

Section: The Phg Packagementioning

confidence: 99%

“…In fact, using SARE, we override the local interconnectivity constraint allowing the generation of synchronous architectures with local and not local interconnections (e.g. data buses) [5,6].…”

Section: The Phg Packagementioning

confidence: 99%

“…which originates the equality p=j (j=-1,…,m-1) (according to [5,6], t is the temporal coordinate and p the processor coordinate in the transformed (time-processor) space). The used projection matrix originates a linear pipeline structure because dependence relation from equation 3, namely from…”

Section: Prosidis Designmentioning

confidence: 99%

See 2 more Smart Citations

PROSIDIS: a special purpose processor for protein similarity discovery

Marongiu¹,

Proceedings International Parallel and Distributed Processing Symposium

Self Cite

A specialized hardware device for the protein similarity search

Marongiu

Concurrency and Computation

2004

Self Cite

SUMMARYThis work presents the architecture of PROSIDIS, a special purpose processor designed to search for the occurrence of substrings similar to a given 'template string' within a proteome. Similarity is determined by means of a weighting matrix which measures the degree of similarity between any two amino acids.The paper recalls the basis of the PHG (Parallel Hardware Generator) tool, developed in the framework of the HADES project (Hardware Design for Scientific Applications). Through PHG it is possible to design, in a nearly automatic way, a parallel hardware which efficiently implements an algorithm described through recurrence equations; PHG is able to generate a synthesizable VHDL which represents a parallel system derived from the System of Affine Recurrence Equations (SARE) describing the problem.In this work we illustrate the advantages derived from designing a special purpose processor to face the protein similarity discovery problem. Some preliminary results are given, reporting the time spent by several conventional computing architectures and by the PROSIDIS processor hosted by a personal computer to solve the same protein analysis problem. The results show that PROSIDIS, implemented on a Xilinx XV1000 FPGA, gives speedup figures ranging from 5.6 up to 55.6.