Automatic Insertion of Low Power Annotations in RTL for Pipelined Microprocessors

Viswanath, Vinod; Abraham, H.A.; Hunt, Warren A.

doi:10.1109/date.2006.243858

Cited by 5 publications

(1 citation statement)

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“…At the one end are low power optimizations implemented by hardware designers like transistor level [2], gate level [11] and RTL optimizations [15], clock and power gating [17], optimizations to the processor pipeline, etc. These optimizations are done quite independent of the rest of the platform components, and in most cases, hardware is the best judge of what optimizations to use.…”

Section: Introductionmentioning

confidence: 99%

On a rewriting strategy for dynamically managing power constraints and power dissipation in SoCs

Viswanath¹,

Muralidhar

Seshadri

et al. 2013

International Symposium on Quality Electronic Design (ISQED)

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We present a novel and highly automated technique for dynamic system level power management of System-on-aChip (SoC) designs. We present a formal system to represent power constraints and power intent as rules. We also present a Term Rewriting Systems based rule rewriting engine as our dynamic power manager. We provide a notion of formal correctness of our rule engine execution and provide a robust algorithm to dynamically and automatically manage power consumption in large SoC designs.There are two fundamental building blocks at the core of our technique. First, we present a powerful formal system to capture power constraints and power intent as rules. This is a selfchecking system and will automatically flag conflicting constraints or rules. Next, we present a rewriting strategy for managing power constraint rules using a formal deductive logic technique specially honed for dynamic power management of SoC designs. Together, this provides a common platform and representation to seamlesslycooperatebetweenhardwareandsoftwareconstraints to achieve maximum platform power optimization dynamically during execution.We demonstrate our technique in multiple contexts on an SoC design of the state-of-the-art next generation Intel smartphone platform.

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Section: Introductionmentioning

confidence: 99%