Automatic implementation of affine iterative algorithms: Design flow and communication synthesis

Marongiu, A.; Palazzari, P.

doi:10.1016/s0010-4655(01)00234-x

Cited by 4 publications

(7 citation statements)

References 22 publications

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“…In fact, using SARE, we override the local interconnectivity constraint allowing the generation of synchronous architectures with local and non-local interconnections (e.g. data buses) [5,6].…”

Section: Introductionmentioning

confidence: 99%

A specialized hardware device for the protein similarity search

Marongiu

Palazzari

Rosato

2004

Concurrency and Computation

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SUMMARYThis work presents the architecture of PROSIDIS, a special purpose processor designed to search for the occurrence of substrings similar to a given 'template string' within a proteome. Similarity is determined by means of a weighting matrix which measures the degree of similarity between any two amino acids.The paper recalls the basis of the PHG (Parallel Hardware Generator) tool, developed in the framework of the HADES project (Hardware Design for Scientific Applications). Through PHG it is possible to design, in a nearly automatic way, a parallel hardware which efficiently implements an algorithm described through recurrence equations; PHG is able to generate a synthesizable VHDL which represents a parallel system derived from the System of Affine Recurrence Equations (SARE) describing the problem.In this work we illustrate the advantages derived from designing a special purpose processor to face the protein similarity discovery problem. Some preliminary results are given, reporting the time spent by several conventional computing architectures and by the PROSIDIS processor hosted by a personal computer to solve the same protein analysis problem. The results show that PROSIDIS, implemented on a Xilinx XV1000 FPGA, gives speedup figures ranging from 5.6 up to 55.6.

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Section: Introductionmentioning

confidence: 99%

A specialized hardware device for the protein similarity search

Marongiu

Palazzari

Rosato

2004

Concurrency and Computation

View full text Add to dashboard Cite

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“…The PHG theoretical framework is described in [5,6] while the detailed theory is reported in [7]. The PHG is based on the design flow shown in figure 1.…”

Section: The Phg Packagementioning

confidence: 99%

“…In fact, using SARE, we override the local interconnectivity constraint allowing the generation of synchronous architectures with local and not local interconnections (e.g. data buses) [5,6].…”

Section: The Phg Packagementioning

confidence: 99%

“…Finally, due to the elimination of the local interconnection constraint, a new methodology has been formulated [5] in order to minimize the resources needed to implement not local communications.…”

Section: The Phg Packagementioning

confidence: 99%

“…which originates the equality p=j (j=-1,…,m-1) (according to [5,6], t is the temporal coordinate and p the processor coordinate in the transformed (time-processor) space). The used projection matrix originates a linear pipeline structure because dependence relation from equation 3, namely from…”

Section: Prosidis Designmentioning

confidence: 99%

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