Automatic generation of synchronous test patterns for asynchronous circuits

Abstract

This paper presents a novel approach for automatic test pattern generation of asynchronous circuits. The techniques used for this purpose assume that the circuit can only be exercised by applying synchronous test vectors, as is done by real-life testers. The main contribution of the paper is the abstraction of the circuit's behavior as a synchronous finite state machine in such a way that similar techniques to those currently used for synchronous circuits can be safely applied for testing. Currently, the fault model being used is the input stuck-at model. Experimental results on different benchmarks show that our approach generates test vectors with high fault coverage.

Fault simulation and random test generation for speed-independent circuits

“…The total number of stuck-at faults before collapsing, after collapsing, and the collapsing rate for each circuit are listed in the second, third, and fourth columns, respectively. Note that the number of total faults for each circuit is normally larger than that in [11], because we substituted complex gates with gate-level implementations, hence there are more gates and more possible faults in each circuit. Unfortunately some of the new faults have been proven to be redundant.…”

“…Several researchers [1,2,11] studied the problem of testing asynchronous circuits using available commercial testers for synchronous circuits. In order to avoid uncertainty, fault effects have to be observed when the circuit is in a stable state.…”

“…Hence, simple time-frame unfolding simulation methods for Huffman circuits might be invalid for these circuits, since they ignore the additional race conditions and hazards imposed by changes of state signals before the circuit has stabilized. Eichelberger's method [7] for simulation of sequential circuits can be adapted for simulation of Speed-Independent circuits as in [11], but it is unacceptably conservative to be used for a fault simulator. In many cases, it fails to determine the actual circuit state and simply reports an unknown state.…”

Characterization of Asynchronous Templates for Integration into Clocked CAD Flows

“…There are a number of current research and industrial efforts focusing on this promising flow. Desynchronization supports Verilog and uses a template based approach, and algorithms have been developed for test generation [14]. However, this flow does not support general asynchronous design, largely due to the low number of asynchronous templates and custom tools.…”

Partial scan delay fault testing of asynchronous circuits

“…We assume that the information about which delays in the manufactured circuit must be tested to ensure correct operation is available (e.g., from the synthesis tools). Previous work in the area of asynchronous circuit testing either used greedy heuristic techniques ( [4]) to justify and propagate stuck-at faults, or used exhaustive synchronous mode testing for stuck-at faults ( [3,19]) or used manual transformations to ensure that a simple functional testing approach could test all stuck-at faults ( [20]), or used a fullscan approach to robustly test all delay faults ( [8,12,17]). …”