Automatic generation of microarchitecture simulators

Önder, Soner; Gupta, Rajiv

doi:10.1109/iccl.1998.674159

Cited by 42 publications

(28 citation statements)

References 5 publications

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“…Since we do not have the appropriate cross-compiler, Fortran 90 and C++ benchmarks in the SPEC2000 suite have been excluded. The architectural simulators used in this study are written in the ADL language [16] and automatically generated by the FAST simulation system. Simulators model the basic superscalar pipeline shown in Figure 10 and are cycle accurate.…”

Section: Experimental Methodologymentioning

confidence: 99%

Fast branch misprediction recovery in out-of-order superscalar processors

Zhou

Önder

Carr

2005

Proceedings of the 19th Annual International Conference on Supercomputing

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Current trends in modern out-of-order processors involve implementing deeper pipelines and a large instruction window to achieve high performance. However, as pipeline depth increases, the branch misprediction penalty becomes a critical factor in overall processor performance. Current approaches to handling branch mispredictions either incrementally roll back to in-order state by waiting until the mispredicted branch reaches the head of the reorder buffer, or utilize checkpointing at branches for faster recovery. Rolling back to in-order state stalls the pipeline for a significant number of cycles and checkpointing is costly.This paper proposes a fast recovery mechanism, called Eager Misprediction Recovery (EMR), to reduce the branch misprediction penalty. Upon a misprediction, the processor immediately starts fetching and renaming instructions from the correct path without restoring the map table. Those instructions that access incorrect speculative values wait until the correct data are restored; however, instructions that access correct values continue executing while recovery occurs. Thus, the recovery mechanism hides the latency of long branch recovery with useful instructions.EMR achieves a mean performance improvement very close to a recovery mechanism that supports checkpointing at each branch. In addition, EMR provides an average of 9.0% and up to 19.9% better performance than traditional sequential misprediction recovery on the SPEC2000 benchmark suite.

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Section: Experimental Methodologymentioning

confidence: 99%

Fast branch misprediction recovery in out-of-order superscalar processors

Zhou

Önder

Carr

2005

Proceedings of the 19th Annual International Conference on Supercomputing

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“…The challenge is to produce a sound and complete set of constraints for a given simulator implementation so that the correctness of the simulator can be trusted with high confidence. We have developed a large number of constraints targeting these common errors in modeling and tested two simulators, one automatically synthesized from an Architecture Description Language (ADL) [12] specification and the other for SimpleScalar out-of-order simulator [16]. Both of these simulators model sophisticated superscalar processor architectures.…”

Section: Constraint Examplesmentioning

confidence: 99%

“…The data traces were obtained from FAST ADL [12] and SimpleScalar out of order [16] simulators. We manually instrumented various events in FAST ADL simulator.…”

Section: Case Studiesmentioning

confidence: 99%

Verifying micro-architecture simulators using event traces

Nyew

Onder

Önder

et al. 2014

Proceedings of the 28th ACM International Conference on Supercomputing

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Contemporary micro-architecture research inherently relies on cycleaccurate simulators to test new ideas. Typical simulator implementations involve tens of thousands of lines of high-level code. Although general software engineering verification and validation techniques can be applied, the mere complexity of simulators makes using formal techniques difficult and calls for domain-specific knowledge to be a part of the verification process. This domain-specific information includes modeling the pipeline stages and the timing behavior of instructions with respect to these stages.We present an approach to simulator verification that uses domainspecific information to effectively capture a potential mismatch between the assumed architecture model and its simulator. We first discuss how a simulator-generated event trace can be fed into an automatically generated verification program from a first-order logic specification to verify that the simulator obeys the invariants. We then show techniques that extract simulator behavior from traces and present the results to the user in the form of graphs and rules. While the former seeks an assurance of implementation correctness by checking that the model invariants hold, the latter attempts to derive an extended model of the implementation and hence enables a deeper understanding of what was implemented.Our techniques are applicable to any micro-architecture simulator. We present the application of our techniques to hand-written simulators as well as to those generated from an architecture specification language.

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“…To examine the performance of memory distance based memory disambiguation, we use the FAST micro-architectural simulator based upon the MIPS instruction set [16]. The simulated architecture is an out-of-order superscalar pipeline which can fetch, dispatch and issue 8 operations per cycle.…”

Section: Experimental Designmentioning

confidence: 99%