Automatic generation of interfaces for distributed C-VHDL cosimulation of embedded systems: an industrial experience

Valderrama, Carlos; Nacabal, F.; Paulin, Pierre; Jerraya, Ahmed

doi:10.1109/iwrsp.1996.506730

Cited by 19 publications

(7 citation statements)

References 17 publications

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“…The key to the methodology is the presence of a co-simulation approach which allows the simulation of C code on the behavioral level integrated with a VHDL model of the system [67][80] [104]. Individual simulations of the system replacing the co-simulation model with a VHDL model of the processor generates two simulation traces which can be compared.…”

Section: Resultsmentioning

confidence: 99%

“…These technologies include the areas of hardware-software estimation and partitioning [51] [42], hardware-software co-simulation (e.g. VHDL-C co-simulation) [80] [104], behavioral synthesis of hardware [14], and processor design and synthesis. While we recognize the importance of these areas, these subjects are beyond the scope of this text.…”

Section: Ask the Usersmentioning

confidence: 99%

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Retargetable Compilers for Embedded Core Processors

Liem

1997

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Section: Resultsmentioning

confidence: 99%

Section: Ask the Usersmentioning

confidence: 99%

Retargetable Compilers for Embedded Core Processors

Liem

1997

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“…Early HW/SW cosimulation environments were heterogeneous simulation environments where the HDL simulator and processor simulator communicate with each other using interprocess communication (IPC) [4], [5]. In connecting heterogeneous simulators, the cosimulation backplane approach is presented in [6] as opposed to pairwise-direct coupling.…”

Section: Related Workmentioning

confidence: 99%

Fast and Accurate Cosimulation of MPSoC Using Trace-Driven Virtual Synchronization

Kim²,

2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-As MPSoC has become an effective solution to everincreasing design complexity of modern embedded systems, fast and accurate cosimulation of such systems is becoming a tough challenge. Cosimulation performance is in inverse proportion to the number of processor simulators in conventional cosimulation frameworks with lock-step synchronization schemes. To overcome this problem, we propose a novel time synchronization technique called trace-driven virtual synchronization. Having separate phases of event generation and event alignment in the cosimulation, time synchronization overhead is reduced to almost zero, boosting cosimulation speed while accuracy is almost preserved. In addition, this technique enables (1) a fast mixed level cosimulation where different abstraction level simulators are easily integrated communicating with traces and (2) a distributed parallel cosimulation where each simulator can run at its full speed without synchronizing with other simulator too frequently. We compared the performance and the accuracy with MaxSim, a well-known commercial SystemC simulation framework, and the proposed framework showed 11 times faster performance for H.263 decoder example, while the error was below 5%.

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“…Much work has been done to solve communication gaps for hardware/software co-simulation, mostly focused on the register transfer level such as ISS and HDL. The existing solutions are usually targeting some particular design languages or simulators, and the connections across different platforms are usually done manually [3,14,9]. In this work, our focus is a generic co-design framework for heterogeneous design components regardless if they are software, hardware, or both.…”

Section: Related Workmentioning

confidence: 99%

Communication and Co-Simulation Infrastructure for Heterogeneous System Integration

Yang

Chen

Balarin

et al. 2006

Proceedings of the Design Automation &Amp; Test in Europe Conference

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With the increasing complexity and heterogeneity of embedded electronic systems, a unified design methodology at higher levels of abstraction becomes a necessity. Meanwhile, it is also important to incorporate the current design practice emphasizing IP reuse at various abstraction levels. However, the abstraction gap prohibits easy communication and synchronization in IP integration and co-simulation. In this paper, we present a communication infrastructure for an integrated design framework that enables co-design and cosimulation of heterogeneous design components specified at different abstraction levels and in different languages. The core of the approach is to abstract different communication interfaces or protocols to a common high level communication semantics. Designers only need to specify the interfaces of the design components using extended regular expressions; communication adapters can then be automatically generated for the co-simulation or other co-design and co-verification purposes.

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Automatic generation of interfaces for distributed C-VHDL cosimulation of embedded systems: an industrial experience

Cited by 19 publications

References 17 publications

Retargetable Compilers for Embedded Core Processors

Retargetable Compilers for Embedded Core Processors

Fast and Accurate Cosimulation of MPSoC Using Trace-Driven Virtual Synchronization

Communication and Co-Simulation Infrastructure for Heterogeneous System Integration

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