Retargetable Compilers for Embedded Core Processors

Liem, Clifford

doi:10.1007/978-1-4757-6422-2

Cited by 46 publications

(13 citation statements)

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“…This memory is configured as a dual-bank for a Harvard architecture that allows simultaneous program and data memory access [6]. Recently, several DSP products, such as Analog Device ADSP2100, DSP Group PineDSPCore, Motorola DSP56000 and NEC uPD77016, have even enhanced the original design of the Harvard architecture by providing one additional data bank.…”

Section: Introductionmentioning

confidence: 99%

Run-Time Memory Optimization for DDMB Architecture Through a CCB Algorithm

Cho

Paek

2006

Emerging Directions in Embedded and Ubiquitous Computing

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Abstract. Most vendors of digital signal processors (DSPs) support a Harvard architecture, which has two or more memory buses, one for program and one or more for data and allow the processor to access multiple words of data from memory in a single instruction cycle. We already addressed how to efficiently assign data to multi-memory banks in our previous work. This paper reports on our recent attempt to optimize run-time memory. The run-time environment for dual data memory banks (DDMBs) requires two run-time stacks to control activation records located in two memory banks corresponding to calling procedures. However, activation records of two memory banks for a procedure are able to have different size. As a consequence, dual run-time stacks can be unbalanced whenever a procedure is called. This unbalance between two memory banks causes that usage of one memory bank can exceed the extent of on-chip memory area although there is free area in the other memory bank. We attempt balancing dual run-time stacks to enhance efficiently utilization of onchip memory in this paper. The experimental results have revealed that although our call chain balancing (CCB) algorithm is relatively quite simple, it still can utilize run-time memories efficiently; thus enabling our compiler to run extremely fast, yet minimizing the usage of run-time memory in the target code.

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Section: Introductionmentioning

confidence: 99%

Run-Time Memory Optimization for DDMB Architecture Through a CCB Algorithm

Cho

Paek

2006

Emerging Directions in Embedded and Ubiquitous Computing

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“…7 Thus, we expect the above theoretical asymptotic complexity to be very pessimistic for the class of problems of interest. For all the DSP benchmarks considered in x5, the total execution time has never exceeded 0:5 sec on an UltraSparc 1.…”

Section: Cost Of O(l)mentioning

confidence: 99%

“…Code generation for VLIW ASIPs has been addressed extensively in the literature, see e.g., [8,7]. Although discussing this work is beyond the scope of this paper, to further illustrate the relevance of the trade-off information captured by the WDG, we will briefly discuss the AVIV code generator [4].…”

Section: Dfgmentioning

confidence: 99%

“…While some of the bounding approaches give tight bounds when applied to datapaths with a centralized register file, they may be uninformative when applied to datapaths with distributed register file structures, see e.g., Fig.1. Since the datapaths of Very Large Instruction Word (VLIW) ApplicationSpecific Instruction-Set Processors (ASIPs) typically exhibit such distributed storage structures [8,7], there is a need to develop bounds that can be informative in this context. These bounds can in turn provide guidance during code generation for this important class of embedded processors -in particular, as discussed in the sequel, during the functional unit binding (assignment) phase of code generation.…”

Section: Introductionmentioning

confidence: 99%

“…In particular, we will focus on DFGs corresponding to single basic blocks within a loop body, since these are typically the time critical segments for the embedded applications and are likely to benefit the most from using VLIW ASIPs [8,7].…”

Section: Introductionmentioning

confidence: 99%

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Lower bound on latency for VLIW ASIP datapaths

Jacome¹,

Veciana²

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)

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Traditional lower bound estimates on latency for dataflow graphs assume no data transfer delays. While such approaches can generate tight lower bounds for datapaths with a centralized register file, the results may be uninformative for datapaths with distributed register file structures that are characteristic of VLIW ASIPs. In this paper we propose a latency bound that accounts for such data transfer delays. The novelty of our approach lies in constructing the "window dependency graph" and bounds associated with the problem which capture delay penalties due to operation serialization and/or data moves among distributed register files. Through a set of benchmark examples, we show that the bound is competitive with state-of-the-art approaches. Moreover, our experiments show that the approach can aid an iterative improvement algorithm in determining good functional unit assignments -a key step in code generation for VLIW ASIPs.

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