Automatic Functional Stress Pattern Generation for SoC Reliability Characterization

Appello, D.; Bernardi, P.; Cagliesi, R.; Giancarlini, M.; Grosso, M.; Sánchez, Ernesto; Reorda, M. Sonza

doi:10.1109/ets.2009.16

Cited by 6 publications

(9 citation statements)

References 13 publications

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“…Table I, shows the best stress patterns results of each SoC module, which were generated and evaluated by the two-phase strategy. In order to provide comparative results among the suggested approach and the previous methodology in [9], both procedures were launched at the same time. A preliminary stress quality level was reached by the proposed approach at around 190 hours of continuously pattern generation and evaluation, and then results of both methodologies were compared.…”

Section: Case Study and Resultsmentioning

confidence: 99%

“…Such programs are referred as functional stress patterns. With respect to [9], where only gate-level simulations are employed, we propose an EA based methodology that achieves better results in a shorter time.…”

Section: Proposed Approachmentioning

confidence: 99%

“…Each individual is characterized by a quality value called fitness that is computed by an evaluator. An EA based methodology for the automatic generation of functional stress patterns is introduced in [9]. Even though the method achieved good results, it is highly time consuming, since the evaluation step is based on slow gatelevel simulations.…”

Section: Functional Program Generation Approach By Means Of Evolutionmentioning

confidence: 99%

“…In this paper, we concentrate on generating stress patterns for an effective SoC stress phase during OLT phases; similarly to the previous work [9], such patterns are functional test programs executed by the programmable resources available on chip, which maximizes the switching activity while complying with the IC's normal functionalities. In the approach, the quality of the stress program under generation is calculated using some suitable metrics which are strictly related to the toggle activity of the circuit; these metrics, already discussed in [8], suit to measure how strong and uniform is the applied functional stress.…”

Section: Introductionmentioning

confidence: 98%

“…The benefits in terms of time gained with respect to the previous approach introduced in [9] are evaluated on a 90nm technology System-on-Chip including an 8051 microcontroller core. Experimental results show that the generation time is reduced significantly and high stress quality is achieved in a short time.…”

Section: Introductionmentioning

confidence: 99%

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An Enhanced Strategy for Functional Stress Pattern Generation for System-on-Chip Reliability Characterization

Carvalho

Bernardi

Sánchez

et al. 2010

2010 11th International Workshop on Microprocessor Test and Verification

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Reliability characterization is the industrial process intended to measure the useful life period and failure rate of a component population by exploiting stress mechanisms.The paper describes a methodology for the automatic generation of stress programs to be used during the reliability characterization process of Systems-on-Chip (SoC). The proposed methodology is composed of a twophase strategy; first an evolutionary algorithm (EA) works on the SoC's description at Register-Transfer-Level (RTL) by evaluating high-level metrics to quickly progress to a sufficient stress quality level; then evolution is continued on the gate-level description towards a better stress quality.The proposed methodology was experimented on a SoC manufactured in a 90nm technology including an 8051 processor. The proposed strategy reduces significantly the generation times and quickly improves the stress quality values with respect to the previous methodology.

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Section: Case Study and Resultsmentioning

confidence: 99%

Section: Proposed Approachmentioning

confidence: 99%

Section: Functional Program Generation Approach By Means Of Evolutionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 98%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

An Enhanced Strategy for Functional Stress Pattern Generation for System-on-Chip Reliability Characterization

Carvalho

Bernardi

Sánchez

et al. 2010

2010 11th International Workshop on Microprocessor Test and Verification

Self Cite

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Improving Stress Quality for SoC Using Faster-than-At-Speed Execution of Functional Programs

Bernardi

Bosio

Natale

et al. 2017

IFIP Advances in Information and Communication Technology

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At the end of the manufacturing cycle of digital circuits, a stress phase is mandatory in order to remove from the final device population the weak devices that may result in early life failures. Devices used in safety critical environments must undergo this phase that is usually accomplished by exploiting the Burn-In (BI) process. Unfortunately, BI has elevated costs for companies and current state of the art techniques are trying to reduce its cost. In recent days, Faster-than-at-Speed-Test (FAST) has become a useful technique to discover small delay defects. At the same time, overclocking methods to enhance system performances have been studied, which focus on temperature management to preserve system functionalities. In this contribution, a FAST technique is proposed with the aim of intentionally provoking a thermal overheating in the microprocessor by mean of the execution of FAST functional test programs; in other words, functional procedures are executed at higher than nominal frequencies. The goal is to introduce an internal stress stronger than current procedures used during BI in order to speed up early detection of latent faults. Being the functional stress procedures executed at faster than nominal speed, the original behaviour may not be preserved and therefore non-functional states may be reached. In this contribution, it is illustrated how to avoid blocking configurations due to timing constraints violation and how to obtain a significant increase of the switching activity by carefully increasing the clock frequency. Furthermore, a novel strategy is proposed to generate a suitable set of Faster-than-At-Speed stress programs capable to thoroughly stress processor cores. Experimental results carried out on a MIPS-like architecture show major achievements of the methodology: the processor may work at frequencies up to about 20 times higher than the nominal one without falling into an unpredictable state and the switching activity is increasing up to 300% per nanoseconds.

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A Toolchain to Quantify Burn-In Stress Effectiveness on Large Automotive System-on-Chips

Angione,

Appello,

Bernardi

et al. 2023

IEEE Access

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Complexity and performance of Automotive System-on-Chips have exponentially grown in the last decade, also according to technology advancements. Unfortunately, this trend directly and profoundly impacts modern Electronic Design Automation tools, which must handle very large amounts of logic gates. The consequence is an exponential increase in computation times, potentially leading to significant production delays. In the context of Burn-In, to reduce the computing time, the stress specification is often relaxed due to the difficulty of grading extensive pattern sets, and it may result in the insurgence of unstressed circuit zones. As a matter of fact, current Electronic Design Automation software tools provide limited capabilities to effectively quantify stress effectiveness, investigate perpattern set coverage loss, and compute layout-aware stress metrics. This article proposes a toolchain to overcome the limitations mentioned above. We propose a complete software flow to evaluate Burn-In stress patterns through standard toggle coverage and activity effectively. Together with these standard metrics, this article illustrates how to complement traditional measurement with layout-aware toggle coverage metrics. By exploiting parallel programming paradigms and machine learning algorithms, the proposed toolchain drastically reduces computation time for evaluating traditional stress metrics, and it offers new analysis metrics to test engineers conceiving the Burn-in stress patterns. In addition, the toolchain offers some commodities to superimpose the generated stress from different patterns and visualize it over the SoC layout through a heatmap, providing great benefits to test engineers in charge of composing Burn-In recipes. We validated our toolchain on two industrial devices from STMicroelectronics belonging to the SPC58 and SPC56 families, which include around 20 million and 2.7 million gates, respectively.

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Automatic Functional Stress Pattern Generation for SoC Reliability Characterization

Cited by 6 publications

References 13 publications

An Enhanced Strategy for Functional Stress Pattern Generation for System-on-Chip Reliability Characterization

An Enhanced Strategy for Functional Stress Pattern Generation for System-on-Chip Reliability Characterization

Improving Stress Quality for SoC Using Faster-than-At-Speed Execution of Functional Programs

A Toolchain to Quantify Burn-In Stress Effectiveness on Large Automotive System-on-Chips

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