Automatic FSM Synthesis for Low‐power Mixed Synchronous/Asynchronous Implementation

Abstract

Power consumption in a synchronous FSM (Finite-State Machine) can be reduced by partitioning it into a number of coupled sub-FSMs where only the part that is involved in a state transition is clocked. Automatic synthesis of a partitioned FSM includes a partitioning algorithm and sub-FSM synthesis to an implementation architecture. In this paper, we first introduce an implementation architecture for partitioned FSMs that uses gated-clock technique for disabling idle parts of the circuits and asynchronous controllers for communication between the sub-FSMs. We then describe a new transformation procedure for the sub-FSM. The FSM synthesis flow has been automated in a prototype tool that accepts an FSM specification. The tool generates synthesizable RT-level VHDL code with identical cycle-to-cycle input/output behavior in accordance with the specification. An average power reduction of 45% has been obtained for a set standard FSM benchmarks.

Mixed synchronous/asynchronous state memory for low power FSM design

“…This makes crossing transitions more power consuming than local transitions. The work by Oelmann et al [10] introduces a mechanism that makes the crossing transition asynchronously and thereby removes the double-clocking requirement, which leads to lower power consumption. This approach leads however to large area overhead mainly due to complex asynchronous logic and large overhead in the output logic.…”

Asynchronous burst-mode control for low-power gated-clock finite state machines

“…We can classify two types of mechanisms that are used in the gated-clock architecture to activate and deactivate sub-FSMs (communication between sub-FSMs): synchronous communication and asynchronous communication. Oelmann et al [10,11] propose a clock controller block (CCB) to perform asynchronous communication (see Fig. 1).…”

An approach to synthesis of mixed synchronous/asynchronous digital devices

“…To synthesize designs at register-transfer level the model of a finite state machine with datapath (FSMD) is introduced in [4]. The FSMD computes new values for variables stored in the data-path and produces outputs.…”

“…In this case, the locally-synchronous module, performing the desired functionality is equipped with an asynchronous wrapper that contains a controller for each input/output port and a clock generator [9]. The feature of architecture used in [4] for low power synthesis is that the communication among the sequential components is handled by clock control blocks. Clock control block (CCB) provides realization of activation and disactivation of associated sequential component.…”

“…As distinct from previous work [3], [4] in this paper conceptually more general theoretical background for partition is presented and corresponding procedure of partition is outlined.…”