Automatic Fault Localization for Property Checking

Staber, Stefan; Fey, Görschwin; Bloem, Roderick; Drechsler, Rolf

doi:10.1007/978-3-540-70889-6_4

Cited by 9 publications

(9 citation statements)

References 22 publications

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“…These techniques can suffer from a large number of false positives, and return too many candidate error sites. To address this problem, recent work by Staber et al [23] inserts multiplexers explicitly into the RTL code. This enables the use of hardware analysis techniques and greatly improves the accuracy of diagnosis.…”

Section: Automatic Diagnosismentioning

confidence: 99%

Debugging strategies for mere mortals

Bertacco

2009

Proceedings of the 46th Annual Design Automation Conference

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Recent improvements in design verification strive to automate error detection and greatly enhance engineers' ability to detect functional errors. However, the process of diagnosing the cause of these errors, and subsequently fixing them, remains one of the most difficult tasks of verification. The complexity of design descriptions, paired with the scarcity of software tools supporting this task lead to an activity that is mostly ad-hoc, labor intensive and accessible only to a few debugging specialists within a design house. This paper discusses some recent research solutions that support the debugging effort by simplifying and automating bug diagnosis. These novel techniques demonstrate that, through the support of structured methodologies, debugging can become a task pursued by the average design engineer. We also outline some of the upcoming trends in design verification, postponing some the verification effort to runtime, and discuss how debugging could leverage these trends to achieve better quality of results.

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Section: Automatic Diagnosismentioning

confidence: 99%

Debugging strategies for mere mortals

Bertacco

2009

Proceedings of the 46th Annual Design Automation Conference

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“…The new approach "borrows" ideas that were originally proposed for diagnosis based on SAT [11,12]. During diagnosis a modification of the circuit is needed that allows to correct faulty behavior.…”

Section: Theorem 1 a Circuit C And A Set Of Faulty Circuits C Csf mentioning

confidence: 99%

“…The reported data are the same as previously with the exception of #cmp and |C|. Here, the problem instances were derived from Verilog code and an expression in the Verilog code was considered as a single component [12].…”

Section: Robust Circuitsmentioning

confidence: 99%

A Basis for Formal Robustness Checking

Fey

Drechsler

2008

9th International Symposium on Quality Electronic Design (Isqed 2008)

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“…Several existing error-diagnosis techniques are able to identify the RTL code statements that may be responsible for the design errors [11,16,18,20]. Unlike these techniques, REDIR returns the RTL variables that are responsible for the errors instead.…”

Section: Identifying Erroneous Code Statementsmentioning

confidence: 99%

“…However, these techniques can return large potential error sites. To address this problem, a recent work by Staber et al [20] explicitly inserts MUXes into the HDL code. This approach allows the use of hardware analysis techniques and greatly improves the accuracy of error diagnosis.…”

Section: Introductionmentioning

confidence: 99%