Automatic Data Path Synthesis

Thomas, D. S.; Hitchcock,; Kowalski,; Rajan,; Walker, Trent

doi:10.1109/mc.1983.1654268

Cited by 85 publications

(11 citation statements)

References 10 publications

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“…Thus data-dependent loops, especially those that cannot be unfolded, are not supported in most systems that employ value-based approaches for register optimization. REAL [Kurdahi and Parker 1987], EMUCS [Thomas et al 1983], and EASY [Stok and Born 1988] use value-based register optimization techniques. REAL [Kurdahi and Parker 1987], which is part of the ADAM system [Granacki et al 1985], uses the Left Edge Algorithm for interval graphs [Hasimoto and Stevens 1971].…”

Section: Related Researchmentioning

confidence: 99%

An efficient register optimization algorithm for high-level synthesis from hierarchical behavioral specifications

Vemuri

Katkoori

Kaul

et al. 2002

ACM Trans. Des. Autom. Electron. Syst.

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We address the problem of register optimization that arises during high-level synthesis from modular hierarchical behavioral specifications. Register optimization is the process of grouping carriers such that each group can be safely allocated to a hardware register. Global register optimization by inline expansion involves flattening the module hierarchy and using a heuristic register optimization procedure on the flattened description. Although inline expansion yields a near-optimal number of registers, it is very time consuming due to the large number of carrier compatibility relationships that must be considered. We present an efficient register optimization algorithm that achieves nearly the same effect of inline expansion without actually inline expanding. The distinguishing feature of the proposed algorithm is that it employs a hierarchical optimization phase which effectively exploits the properties of the module call graph and information gathered during local carrier lifecycle analysis of each module. Experimental results on a number of benchmarks show that the proposed algorithm produces nearly the same number of registers as inline expansion based global optimization and is faster by a factor of 7.0.

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Section: Related Researchmentioning

confidence: 99%

An efficient register optimization algorithm for high-level synthesis from hierarchical behavioral specifications

Vemuri

Katkoori

Kaul

et al. 2002

ACM Trans. Des. Autom. Electron. Syst.

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“…Languages for finite state machines include Hennessy's SLIM (see [42]), Trickey's and Ullman's regular expression language (see [42]), and Silc. Silicon compilation of data paths from high-level languages is discussed in [35], [36], and [41]. Even modern programming lan guages, such as Ada, have been considered as silicon compilation languages [29], [39].…”

Section: Architectural Behavioralmentioning

confidence: 99%

“…However, decades of research have not yet produced general-purpose automatic programming systems. Examples of behavioral silicon compilers are the automatic data-path synthesis system described in [41], which uses ISPS as an input language, and the Ada* silicon compiler [29], [39], which is under study at the University of Utah.…”

Section: Functional Approach To Silicon Compilationmentioning

confidence: 99%

Approaches toward silicon compilation

Goldberg¹,

Hirschhorn²,

Lieberheer³

1985

IEEE Circuits Devices Mag.

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“…This VT eventually became the substructure for the second generation CMUDA system [29], which evolved into the SAW.…”

Section: Introductionmentioning

confidence: 99%

Formal analysis of correctness of behavioral transformations

McFarland

1993

Form Method Syst Des

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Abstract. Much has been said about the importance of formal verification in hardware synthesis, but little has been done. Where it has been applied at all, it has only been used on simple, idealized examples. This paper describes the application of formal semantic analysis and verification to part of a working high-level synthesis system. The process revealed several significant errors in that system, errors that had previously been undetected. This experience leads to some reflections on the need for a rigorous, formal basis for hardware specification and synthesis, and on the value of formal techniques.

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Automatic Data Path Synthesis

Cited by 85 publications

References 10 publications

An efficient register optimization algorithm for high-level synthesis from hierarchical behavioral specifications

An efficient register optimization algorithm for high-level synthesis from hierarchical behavioral specifications

Approaches toward silicon compilation

Formal analysis of correctness of behavioral transformations

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