An efficient register optimization algorithm for high-level synthesis from hierarchical behavioral specifications

Abstract

We address the problem of register optimization that arises during high-level synthesis from modular hierarchical behavioral specifications. Register optimization is the process of grouping carriers such that each group can be safely allocated to a hardware register. Global register optimization by inline expansion involves flattening the module hierarchy and using a heuristic register optimization procedure on the flattened description. Although inline expansion yields a near-optimal number of registers, it is very time consuming due to the large number of carrier compatibility relationships that must be considered. We present an efficient register optimization algorithm that achieves nearly the same effect of inline expansion without actually inline expanding. The distinguishing feature of the proposed algorithm is that it employs a hierarchical optimization phase which effectively exploits the properties of the module call graph and information gathered during local carrier lifecycle analysis of each module. Experimental results on a number of benchmarks show that the proposed algorithm produces nearly the same number of registers as inline expansion based global optimization and is faster by a factor of 7.0.

Model and Methodology for the Synthesis of Heterogeneous and Partially Reconfigurable Systems

“…Life periods or intervals are often used in the domain of register allocation and initially help to reduce the amount of registers needed. Such intervals are respected during the scheduling phase and are often solved using graph coloring, e. g., by the left-edge algorithm or similar approaches [13,17,19]. Note that by attaching life periods, there is no fundamental change in the formal model or a reduction to a specific subset necessary.…”

Scalable interprocedural register allocation for high level synthesis

“…Our proposed algorithm achieves a significant, theoretic complexity reduction. The complexity of the algorithm in [21] is O(|V | 2 ), where V is the set of all values to be allocated. Due to the large value of |V |, this complexity is significantly larger than intraprocedural register allocation algorithm.…”

“…In contrast, the complexity of our algorithm is comparable to intraprocedural register allocation, with only a modest overhead of O(|CG|χ), where |CG| is the number of call graph edges, and χ is the chromatic number, or the total number of register used. In practice, our algorithm can achieve hundred time speedup for the benchmarks for which [21] can complete.…”

“…Such spilling cost can be eliminated if an interprocedural register allocator is used. In the context of HLS, Vemuri et al [21] proposed a solution that significantly outperforms the naive solution based on procedure inlining. However, their method cannot scale to large programs, since it requires the construction of conflict relation among all variables in the program, which could be prohibitively large.…”

“…The main difference is the availability, in theory, of unlimited allocation resources, rather than K registers, with the primary optimization goal of reducing the area of the target design. An excellent review of past efforts can be found in [21].…”