Automatic compaction of microcode

Lioy, Antonio; Mezzalama, Marco

doi:10.1016/0141-9331(90)90010-s

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Microcode Compaction1

Data-flow Optimization1

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1997

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Cited by 2 publications

(2 citation statements)

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“…Lioy and Mezzalama [71] have approached the compaction problem by defining pseudo micro-instructions and sequences of micro-operations with source and destination properties. These sequences can then be packed into and upward past pseudo micro-instructions to form real micro-instructions.…”

Section: Microcode Compactionmentioning

confidence: 99%

Retargetable Compilers for Embedded Core Processors

Liem

1997

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Section: Microcode Compactionmentioning

confidence: 99%

Retargetable Compilers for Embedded Core Processors

Liem

1997

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“…For example, the ALU and the ACU can work in parallel if they do not occupy the data bus at the same time. The instruction format provides orthogonal fields for parallel operations, so that compaction is rather straightforward [14]. However, there are cases where data-flow optimizations must be performed in order to best exploit the available parallelism.…”

Section: Data-flow Optimizationmentioning

confidence: 99%

Am embedded system case study

Liem¹,

Cornero²,

Santana³

et al. 1997

Proceedings of the 34th Annual Conference on Design Automation Conference - DAC '97

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This paper outlines a case study at SGS-Thomson Microelec-tronics on the development of a firmware development environment in cooperation with Thomson Consumer Electronics Components. The enviornment is for an embedded processor used for audio decompression algorithms including: MPEG2, Dolby AC-3 Surround, and Dolby Pro-logic. The enabling component of the firmware environment is a retargetable compiler which maps high-level algorithms onto the embedded processor. Although compilation is the critical technology, this experience has shown that it is insufficient and that other supporting design tools are also important. For this project, that environment includes an instruction-set simulator, a source-level debugger, a custom linker, and a compiler validation strategy. The methodologies are outlined in this paper with an emphasis on the lessons learned in this hardware-software team development.

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Automatic compaction of microcode

Cited by 2 publications

References 12 publications

Retargetable Compilers for Embedded Core Processors

Retargetable Compilers for Embedded Core Processors

Am embedded system case study

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