Automatic alignment and testing system for wafer with ball grid array

Chen, Xinxin; Xiao, Chengdi; Li, Junhui; Tian, Qing; Ge, Dasong; Zhu, Wenhui

doi:10.1016/j.ijleo.2016.02.011

Cited by 4 publications

(1 citation statement)

References 17 publications

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“…A lot of chips are accurately bonded on the wafer, and the locations should not exceed the error range to avoid influencing the subsequent test yield of the chip and influencing production capacity (Lin et al, 2011a(Lin et al, , 2011b(Lin et al, , 2011c. Therefore, it is worth discussing and studying how to bond the chip onto a specific position of the wafer accurately and control the error before the chip test (Chen et al, 2016;Li et al, 2013). Furthermore, the proposed system has the following advantages due to its noncontact structure.…”

Section: Introductionmentioning

confidence: 99%

Optical alignment and compensation control of die bonder for chips containing through-silicon vias

Lin

Hung

Chen

et al. 2019

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Purpose This study aims to present an optical alignment and compensation control of die bonder for chips containing through-silicon vias and develop three-dimensional integrated circuit stacked packaging for compact size and multifunction. Design/methodology/approach The machine vision, optical alignment method and sub-pixel technology in dynamic imaging condition are used. Through a comparison of reference image, the chip alignment calibration can improve machine accuracy and stability. Findings According to the experimental data and preliminary results of the analysis, accuracy can be achieved within the desired range, and the accuracy is much better than traditional die bonder equipment. The results help further research in die bonder for chips containing through-silicon vias. Originality/value In subsequent testing of the chip, the machine can simultaneously test multiple chips to save test time and increase productivity.

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