Automated memory-aware application distribution for Multi-processor System-on-Chips

Orsila, Heikki; Kangas, Tero; Salminen, Erno; Hämäläinen, Timo D.; Hännikäinen, Marko

doi:10.1016/j.sysarc.2007.01.013

Cited by 54 publications

(20 citation statements)

References 16 publications

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“…1. The first three experiments, Exp:1, Exp:2 and Exp:3, are soft error-unaware optimization with different design objectives using application task mapping obtained through simulated annealing [13]. Exp:4 is the proposed design optimization.…”

Section: Resultsmentioning

confidence: 99%

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Soft error-aware design optimization of low power and time-constrained embedded systems

Shafik

Al-Hashimi

Chakrabarty

2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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Abstract-In this paper, we examine the impact of application task mapping on the reliability of MPSoC in the presence of single-event upsets (SEUs). We propose a novel soft erroraware design optimization using joint power minimization with voltage scaling and reliability improvement through application task mapping. The aim is to minimize the number of SEUs experienced by the MPSoC for a suitably identified voltage scaling of the system processing cores such that the power is reduced and the specified real-time constraint is met. We evaluate the effectiveness of the proposed optimization technique using an MPEG-2 decoder and random task graphs. We show that for an MPEG-2 decoder with four processing cores, our optimization technique produces a design that experiences 38% less SEUs than soft error-unaware design optimization for a soft error rate of 10 −9 , while consuming 9% less power and meeting a given real-time constraint. Furthermore, we investigate the impact of architecture allocation (varying the number of MPSoC cores) on the power consumption and SEUs experienced. We show that for an MPSoC with six processing cores and a given realtime constraint, the proposed technique experiences upto 7% less SEUs compared to soft error-unaware optimization, while consuming only 3% more power.

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Section: Resultsmentioning

confidence: 99%

“…Usage [13]) power consumption than Exp:4. Note that this reduction in multiprocessor execution time (T M ) in Exp:2 is achieved at the expense of the highest register usage (R).…”

Section: −9mentioning

confidence: 97%

Soft error-aware design optimization of low power and time-constrained embedded systems

Shafik

Al-Hashimi

Chakrabarty

2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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“…The work compares the performance of their SA-mapping algorithms for different heterogeneous architectures. In another similar work [47], proposed by the same author, the SA-mapping algorithm is adopted to optimize usage of on-chip memory buffers. Their work employs a B-level scheduler after the mapping process to schedule tasks on each processor.…”

Section: Mpsoc Design Literature Reviewmentioning

confidence: 99%

Framework for Simulation of Heterogeneous MpSoC for Design Space Exploration

Tafesse

Muthukumar

2013

VLSI Design

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Due to the ever-growing requirements in high performance data computation, multiprocessor systems have been proposed to solve the bottlenecks in uniprocessor systems. Developing efficient multiprocessor systems requires effective exploration of design choices like application scheduling, mapping, and architecture design. Also, fault tolerance in multiprocessors needs to be addressed. With the advent of nanometer-process technology for chip manufacturing, realization of multiprocessors on SoC (MpSoC) is an active field of research. Developing efficient low power, fault-tolerant task scheduling, and mapping techniques for MpSoCs require optimized algorithms that consider the various scenarios inherent in multiprocessor environments. Therefore there exists a need to develop a simulation framework to explore and evaluate new algorithms on multiprocessor systems. This work proposes a modular framework for the exploration and evaluation of various design algorithms for MpSoC system. This work also proposes new multiprocessor task scheduling and mapping algorithms for MpSoCs. These algorithms are evaluated using the developed simulation framework. The paper also proposes a dynamic fault-tolerant (FT) scheduling and mapping algorithm for robust application processing. The proposed algorithms consider optimizing the power as one of the design constraints. The framework for a heterogeneous multiprocessor simulation was developed using SystemC/C++ language. Various design variations were implemented and evaluated using standard task graphs. Performance evaluation metrics are evaluated and discussed for various design scenarios.

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“…In [2], [13], algorithms are presented to derive a schedule from a SDF graph so that the size of the FIFOs between actors is minimized. Another technique proposed in [20], consists of iterating the scheduling and the memory allocation steps and keeping only the schedule whose corresponding memory allocation uses the least memory.…”

Section: Related Workmentioning

confidence: 99%

Memory bounds for the distributed execution of a hierarchical Synchronous Data-Flow graph

Desnos

Pelcat

Nezan

et al. 2012

2012 International Conference on Embedded Computer Systems (SAMOS)

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Abstract-This paper presents an application analysis technique to define the boundary of shared memory requirements of Multiprocessor System-on-Chip (MPSoC) in early stages of development. This technique is part of a rapid prototyping process and is based on the analysis of a hierarchical Synchronous Data-Flow (SDF) graph description of the system application. The analysis does not require any knowledge of the system architecture, the mapping or the scheduling of the system application tasks.The initial step of the method consists of applying a set of transformations to the SDF graph so as to reveal its memory characteristics. These transformations produce a weighted graph that represents the different memory objects of the application as well as the memory allocation constraints due to their relationships. The memory boundaries are then derived from this weighted graph using analogous graph theory problems, in particular the Maximum-Weight Clique (MWC) problem. Stateof-the-art algorithms to solve these problems are presented and a heuristic approach is proposed to provide a near-optimal solution of the MWC problem. A performance evaluation of the heuristic approach is presented, and is based on hierarchical SDF graphs of realistic applications. This evaluation shows the efficiency of proposed heuristic approach in finding near optimal solutions.

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Automated memory-aware application distribution for Multi-processor System-on-Chips

Cited by 54 publications

References 16 publications

Soft error-aware design optimization of low power and time-constrained embedded systems

Soft error-aware design optimization of low power and time-constrained embedded systems

Framework for Simulation of Heterogeneous MpSoC for Design Space Exploration

Memory bounds for the distributed execution of a hierarchical Synchronous Data-Flow graph

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