2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010) 2010
DOI: 10.1109/date.2010.5457042
|View full text |Cite
|
Sign up to set email alerts
|

Soft error-aware design optimization of low power and time-constrained embedded systems

Abstract: Abstract-In this paper, we examine the impact of application task mapping on the reliability of MPSoC in the presence of single-event upsets (SEUs). We propose a novel soft erroraware design optimization using joint power minimization with voltage scaling and reliability improvement through application task mapping. The aim is to minimize the number of SEUs experienced by the MPSoC for a suitably identified voltage scaling of the system processing cores such that the power is reduced and the specified real-tim… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1
1
1

Citation Types

0
4
0

Year Published

2011
2011
2018
2018

Publication Types

Select...
6
2

Relationship

0
8

Authors

Journals

citations
Cited by 8 publications
(4 citation statements)
references
References 13 publications
0
4
0
Order By: Relevance
“…Simulation Workloads. We generate 39 different event analytic dataflows using the Random Task and Resource Graph (RTRG) utility [22], with 4 − 50 vertices each and a fan-out of up to 5 edges. We uniformly sample and assign one of the benchmarked CEP queries to each vertex.…”
Section: Resultsmentioning
confidence: 99%
“…Simulation Workloads. We generate 39 different event analytic dataflows using the Random Task and Resource Graph (RTRG) utility [22], with 4 − 50 vertices each and a fan-out of up to 5 edges. We uniformly sample and assign one of the benchmarked CEP queries to each vertex.…”
Section: Resultsmentioning
confidence: 99%
“…Another approach that targets Single-Event Upsets (SEUs) mitigation is proposed by Shafik et al [2010]. In this approach, task mapping and voltage scaling are utilized to minimize the power consumption while improving the reliability in a homogeneous MPSoC.…”
Section: Hw/sw Reliability Managementmentioning
confidence: 99%
“…Experimental Setup 1) DAG Generation and Static Characteristics: Our evaluation considers a broad collection of synthetically generated DAGs composed out of the CEP queries introduced and benchmarked above. We use the Random Task and Resource Graph (RTRG) tool [39], developed for embedded systems research, to generate dataflows with different numbers of CEP queries (vertices). We generate DAGs with a maximum vertex out-degree of 1-5 edges.…”
Section: B Observations and Analysismentioning
confidence: 99%