Automated design of networks of transport-triggered architecture processors using dynamic dataflow programs

2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

Sanchez

Jääskeläinen

et al. 2014

This paper introduces advanced software synthesis techniques that enhance the implementation of dynamic dataflow programs. These techniques have been implemented into opensource tools and demonstrated on well-known video decoders including one based on the new High Efficiency Video Coding (HEVC) standard. The results show an improvement of more than 100% of the frame-rate over previously proposed implementations, and achieve real-time decoding of high definition video sequences.

Section: Resultsmentioning

confidence: 99%

Efficient software synthesis of dynamic dataflow programs

2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

Sanchez

Jääskeläinen

et al. 2014

“…The software implementations are generated by use of the TTA back-end of Orcc [30], then the generated code is compiled and simulated thanks to the TTA-based Co-design Environment (TCE) [13]. The evaluation is made thanks to the instruction-set simulator including in the TCE.…”

Section: Methodsmentioning

confidence: 99%

“…However, most of the studies do not target multi-core platforms based on distributed memory organization, but platforms such as FPGA/ASIC [4,1,25] and general-purpose processors [29,14]. In previous work [30], we have already implemented an MPEG-4 Visual decoder on a platform composed of TTA processors interconnected by hardware FIFO channels. This approach targets application-specific platforms which makes it much less flexible than our new approach.…”

Section: Related Workmentioning

confidence: 99%

Embedded Multi-Core Systems Dedicated to Dynamic Dataflow Programs

Sanchez²,

Jääskeläinen³

et al. 2014

J Sign Process Syst

Self Cite

Multimedia applications and embedded platforms are both becoming very complex in order to improve user experience. Thus, multimedia developers need high-level methods to automate time-consuming and error-prone tasks. Dynamic dataflow modeling is attractive to describe complex applications, such as video codecs, at a high level of abstraction. This paper presents a dataflow-based design approach to implement video codecs on embedded multi-core platforms. First, we introduce a custom architecture model to design lowpower multi-core chips based on distributed memory and Transport-Triggered Architecture processor cores. Then, we describe software synthesis techniques to improve dynamic dataflow implementations. This methodology has been implemented into open-source tools and demonstrated on video decoders based on the MPEG-4 Visual standard and the new High Efficiency Video Coding standard. The simulations achieve real-time decoding (40FPS) of high definition (720P) MPEG-4 Visual video sequences on a custom multi-core platformWe would like to thank the organizations which have partially funded this work such as the Center for International Mobility (CIMO) and the Academy of Finland (funding decision 253087). We would also give special thanks to the Orcc and TCE communities as a whole for actively participating in the development of the tools which offers solid basements to this work. clocked at 1Ghz, which is an improvement of more than 100% over previously proposed implementations.

“…The entire co-design flow used in these experiments [26] has been implemented using two open-source compilers: Orcc [19] and the TTA-based Codesign Environment (TCE) [7] [24].…”

Section: B Towards Embedded Multi-core Platformmentioning

confidence: 99%

“…Finally, we evaluate the performance of the resulting partition using our full co-design flow [26]. Figure 6 presents the influence of the number of processors on the performance, in frames per second (FPS), to decode QCIF resolution video based on TTA implementation on a Xilinx Virtex 6 platform (XC6VLX240T) with a 100MHz clock frequency.…”

Section: B Towards Embedded Multi-core Platformmentioning

confidence: 99%

Towards run-time actor mapping of dynamic dataflow programs onto multi-core platforms

2013 8th International Symposium on Image and Signal Processing and Analysis (ISPA)

Casseau

Raulet

et al. 2013

Self Cite

The emergence of massively parallel architectures, along with the necessity of new parallel programming models, has revived the interest on dataflow programming due to its ability to express concurrency. Although dynamic dataflow programming can be considered as a flexible approach for the development of scalable applications, there are still some open problems in concern of their execution. In this paper, we propose a low-cost mapping methodology to map dynamic dataflow programs over any multi-core platform. Our approach finds interesting mapping solutions in few milliseconds that makes it doable at regular time by translating it in an equivalent graph partitioning problem. Consequently, a good load balancing over the targeted platform can be maintained even with such unpredictable applications. We conduct experiments across three MPEG video decoders, including one based on the new High Efficiency Video Coding standard. Those dataflow-based video decoders are executed on two different platform: A desktop multi-core processor, and an embedded platform composed of interconnected and tiny Very Long Instruction Word -style processors. Our entire design flow is based on open-source tools. We present the influence of the number of processors on the performance and show that our method obtains a maximum decoding rate for 16 processors.