Automated design flow for applying Triple Modular Redundancy (TMR) in complex digital circuits

Benites, Luis; Kastensmidt, Fernanda Lima

doi:10.1109/latw.2018.8349668

Cited by 26 publications

(9 citation statements)

References 4 publications

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“…The authors in [7] propose an industrial framework that generates single-event upsets, and integrates fault tolerant structures into a VHDL RTL design. In [6], the authors propose an approach for a commercial ASIC design low that integrates triple modular redundancy structures into a target design at netlist level. Our work is implemented as compiler passes based on an open-source hardware compiler framework comprising a variety of transformation passes such as optimization passes.…”

Section: Related Workmentioning

confidence: 99%

Laser attack benchmark suite

Amornpaisannon

Diavastos

Peh

et al. 2020

Proceedings of the 39th International Conference on Computer-Aided Design

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Section: Related Workmentioning

confidence: 99%

Laser attack benchmark suite

Amornpaisannon

Diavastos

Peh

et al. 2020

Proceedings of the 39th International Conference on Computer-Aided Design

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“…Two special cases are widely used. Dual module redundancy also called Duplication with Compare (DWC) and Triple Module Redundancy (TMR) [7], [8]. The first case only allows to detect faults, while the latter fully masks faults.…”

Section: Introductionmentioning

confidence: 99%

Reducing the Complexity of Fault-Tolerant System Amenable to Approximate Computing

Zhu

Schäfer

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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Many applications tolerate errors at their outputs. Some examples include image and digital signal processing applications. At the same time these applications are often used in systems that require high degrees of fault-tolerance. Examples include autonomous driving applications. Thus, in this work we propose a method to reduce the complexity of hardware redundant systems that are amenable to approximate computing such that soft errors outside a maximum specified threshold are detected. This leads to the detection of catastrophic errors, while allowing the system to continue functioning when smaller single event upsets (SEU) occur. The proposed method reduces the complexity of the duplicated module by applying a set of approximations in such a way that the output is guaranteed to operate within a given error range with the exact module. Experimental results show that the proposed approach works well and that area saving between 30% and 19% can be achieved on average for different error ranges compared to the traditional exact duplication with compare approaches.

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“…These applications are implemented on Static Random Access Memory (SRAM)-based FPGA. SRAM FPGA devices are very critical to radiations and this may cause Single Event Effects (SEE) [5], [8], [9]. SEE is the combination of Single Event Transient (SET) and Single Event Upset (SEU).…”

Section: Introductionmentioning

confidence: 99%

Overview of Fault Tolerance Techniques and the Proposed TMR Generator Tool for FPGA Designs

Khatri¹

2020

IJACSA

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The FPGA has been involved in many safety and mission-critical applications in the last few decades. FPGA designs are also critical to errors and failures due to radiations. Fault-tolerant systems should be designed to overcome the effect of faults or failure during the operation of the systems. The primary objective of any fault tolerance technique is to produce a dependable system. Fault tolerance techniques add the capability to perform proper functioning in the presence of a fault. Faulttolerant techniques can detect the faults and correct them, or mask the faults. The overview of the most standard techniques used for FPGA designs is described in the paper. Among them, it is found that the Triple Modular Redundancy (TMR) technique is the most straight forward in terms of implementation and easy to use. The proposed TMR code generator for implementing the FPGA design is also described. These FPGA designs are written in Verilog Hardware Description Language (HDL) at the different abstraction levels.

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Automated design flow for applying Triple Modular Redundancy (TMR) in complex digital circuits

Cited by 26 publications

References 4 publications

Laser attack benchmark suite

Laser attack benchmark suite

Reducing the Complexity of Fault-Tolerant System Amenable to Approximate Computing

Overview of Fault Tolerance Techniques and the Proposed TMR Generator Tool for FPGA Designs

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