Automated Design Error Localization in RTL Designs

Jenihhin, Maksim; Tsepurov, Anton; Tihhomirov, Valentin; Raik, Jaan; Hantson, Hanno; Ubar, Raimund; Bartsch, Gunter; Escobar, JorgeHernan Meza; Wuttke, Heinz-Dietrich

doi:10.1109/mdat.2013.2271420

Cited by 8 publications

(4 citation statements)

References 6 publications

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“…We carried out experiments on 3 VHDL circuits: [17], GCD implementation in VHDL using parallelized Euclidean algorithm and B13 circuit from ITC99 benchmark suite [18]. The characteristics of the circuits are presented in Table 1.…”

Section: Methodsmentioning

confidence: 99%

Stimuli generation framework for testing multiple processes in VHDL

Jusas

Neverdauskas

2014

ITC

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Hardware Description Languages (HDL) like VHDL are used to design and simulate programmable logic devices. Usually the description of the device under test consists of several processes. This concept introduces problems of how to test and verify complex systems. In this paper, we present a new framework called TestBenchMulti that is able to generate test stimuli for parallel VHDL designs. The framework combines Control Flow Graphs (CFGs), extension of Symbolic Execution (SE) and Satisfiability Modulo Theories (SMT) into a sequence of methods to generate stimuli capable of obtaining high code coverage. The experiments were carried out on synthesizable VHDL circuits at the behavioural level. The obtained code coverage results were confirmed in the real implementation using Xilinx FPGA hardware.

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Section: Methodsmentioning

confidence: 99%

Stimuli generation framework for testing multiple processes in VHDL

Jusas

Neverdauskas

2014

ITC

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“…Dynamic slicing technique is used in [19], [20]. The former uses dynamic slicing for statistical bug localization in RTL.…”

Section: Related Workmentioning

confidence: 99%

Accelerating Transient Fault Injection Campaigns by using Dynamic HDL Slicing

Bagbaba

Jenihhin

Raik

et al. 2019

2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

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Along with the complexity of electronic systems for safety-critical applications, the cost of safety mechanisms evaluation by fault injection simulation is rapidly going up. To reduce these efforts, we propose a fault injection methodology where Hardware Description Language (HDL) code slicing is exploited to accelerate transient fault injection campaigns by pruning fault lists and reducing the number of the injections. In particular, the dynamic HDL slicing technique provides for a critical fault list and allows avoiding injections at non-critical time-steps. Experimental results on an industrial core show that the proposed methodology can successfully reduce the number of injections by up to 10 percent and speed-up the fault injection campaigns.

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“…The dedicated rejuvenation stimuli are generated using the evolutionary toolkit µGP. The flow is implemented and demonstrated in the scalable open-source framework zamiaCAD [TSE12], [JEN14]. The advantage of the approach is flexibility for solving the dependencies of impacts by individual gates to the most critical NBTI-induced path delays by using evolutionary optimization processes, thus, enhances the efficiency of aging relaxation.…”

Section: Aging Mitigationmentioning

confidence: 99%

BASTION: Board and SoC test instrumentation for ageing and no failure found

Jutman¹,

Lotz²,

Larsson

et al. 2017

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2017

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This is an overview paper that motivates and describes performed work done in the European Commission funded research project BASTION, which focuses on two critical problems of modern electronics: the No-Fault-Found (NFF) and CMOS ageing. New defect classes contributing to NFF have been identified, including timing related faults (TRF) at board level and intermittent resistive faults (IRF) at IC level. BASTION has addressed the mechanisms of ageing and developed several techniques to improve the longevity of electronic products. Embedded Instrumentation, monitors, and IEEE 1687 standard for reconfigurable scan networks (RSN) are seen as an important leverage that helped mitigating the impact of the above listed problems by facilitating a low-latency, scalable online system health monitoring and error localization infrastructure as well as integration of all heterogeneous technologies into a homogeneous demonstration platform. This paper helps the reader to get a general overview of the work performed and provides a collection of references to publications where the respective research results are described in detail.

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Automated Design Error Localization in RTL Designs

Cited by 8 publications

References 6 publications

Stimuli generation framework for testing multiple processes in VHDL

Stimuli generation framework for testing multiple processes in VHDL

Accelerating Transient Fault Injection Campaigns by using Dynamic HDL Slicing

BASTION: Board and SoC test instrumentation for ageing and no failure found

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