Verification is an important part of the chip design process. Design is usually represented in hardware description language (HDL). Contemporary HDLs have constructs that are characteristic to software programs. Therefore, the methods to automatically generate test for software programs can be applied to generate test for HDL models. One of such methods is symbolic execution. We present a framework to generate test benches for HDL models. The framework combines the methods of symbolic execution and control flow graph, which are usually used in the context of software programs, with finite state machine that is characteristic for HDL models. The framework is implemented in Python programming language. We experimented with ITC'99 benchmark suite and compared the performance of our framework with similar research. Our obtained results outperformed the results taken from similar research.
Hardware Description Languages (HDL) like VHDL are used to design and simulate programmable logic devices. Usually the description of the device under test consists of several processes. This concept introduces problems of how to test and verify complex systems. In this paper, we present a new framework called TestBenchMulti that is able to generate test stimuli for parallel VHDL designs. The framework combines Control Flow Graphs (CFGs), extension of Symbolic Execution (SE) and Satisfiability Modulo Theories (SMT) into a sequence of methods to generate stimuli capable of obtaining high code coverage. The experiments were carried out on synthesizable VHDL circuits at the behavioural level. The obtained code coverage results were confirmed in the real implementation using Xilinx FPGA hardware.
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