AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators

Abstract

Adopting FPGA as an accelerator in datacenters is becoming mainstream for customized computing, but the fact that FPGAs are hard to program creates a steep learning curve for software programmers. Even with the help of high-level synthesis (HLS), accelerator designers still have to manually perform code reconstruction and cumbersome parameter tuning to achieve the optimal performance. While many learning models have been leveraged by existing work to automate the design of efficient accelerators, the unpredictability of modern HLS tools becomes a major obstacle for them to maintain high accuracy. In this paper, we address this problem by incorporating an automated DSE framework-AutoDSE-that leverages a bottleneck-guided gradient optimizer to systematically find a better design point. AutoDSE finds the bottleneck of the design in each step and focuses on high-impact parameters to overcome that, which is similar to the approach an expert would take. The experimental results show that AutoDSE is able to find the design point that achieves, on the geometric mean, 19.9× speedup over one CPU core for Machsuite and Rodinia benchmarks and 1.04× over the manually designed HLS accelerated vision kernels in Xilinx Vitis libraries yet with 26× reduction of their optimization pragmas. With less than one optimization pragma per design on average, we are making progress towards democratizing customizable computing by enabling software programmers design efficient FPGA accelerators.

Bring Your Own Codegen to Deep Learning Compiler

“…Instead of proposing an architecture for application-specific integrated circuit (ASIC), some accelerator developers proposed a parameterized neural network architecture that fits field programmable gate arrays (FPGAs), so that the architecture can be further customized for each deep learning model [9,24,28,39,41]. Specifically, they proposed an architecture "template" with a set of configurable parameters such as process unit (PE) number and buffer sizes.…”