Attainment of low interfacial trap density absent of a large midgap peak in In0.2Ga0.8As by Ga2O3(Gd2O3) passivation

Abstract

The pronounced high interfacial densities of states (Dit) commonly observed around the midgap energy of dielectric/GaAs interfaces are generally considered the culprit responsible for the poor electrical performance of the corresponding inversion-channel metal-oxide-semiconductor field-effect-transistors. In this work, comprehensive Dit spectra as the function of energy [Dit(E)] inside the In0.2Ga0.8As band gap were constructed by using the quasistatic capacitance-voltage and the temperature-dependent conductance method on n- and p-type ultrahigh vacuum (UHV)-Ga2O3(Gd2O3)/In0.2Ga0.8As and atomic-layer-deposited (ALD)-Al2O3/In0.2Ga0.8As metal-oxide-semiconductor capacitors. Unlike the ALD-Al2O3/In0.2Ga0.8As interface giving a Dit spectrum with a high midgap Dit peak, the UHV-Ga2O3(Gd2O3)/In0.2Ga0.8As interface shows a Dit spectrum that monotonically decreases from the valence band to the conduction band with no discernible midgap peak.

Electrical properties of GaAs metal–oxide–semiconductor structure comprising Al2O3 gate oxide and AlN passivation layer fabricated in situ using a metal–organic vapor deposition/atomic layer deposition hybrid system

“…The improved interface quality obtained in this work was compatible to that obtained in works using in situ ultra-high vacuum processes. 17,18 Additionally, using a (111)A substrate effectively reduced the frequency dispersion of accumulation capacitance, thereby suggesting the suppression of traps in GaAs located near the dielectric/GaAs interface. Further improvements in the interface quality are expected to unveil superior charge transport properties of GaAs.…”

“…One solution is the use of an ultra-high vacuum (UHV) process, whereby both III-V epitaxy and dielectric deposition are performed under UHV. [15][16][17][18] As reported, Ga 2 O 3 (Gd 2 O 3 )/In 0.2 Ga 0.8 As and Al 2 O 3 /GaAs interfaces prepared using UHV exhibit low D it around midgap. 17,18 However, the UHV approach requires a multi-chamber UHV equipment that is impractical for industrial manufacturing.…”

“…[15][16][17][18] As reported, Ga 2 O 3 (Gd 2 O 3 )/In 0.2 Ga 0.8 As and Al 2 O 3 /GaAs interfaces prepared using UHV exhibit low D it around midgap. 17,18 However, the UHV approach requires a multi-chamber UHV equipment that is impractical for industrial manufacturing. In contrast, atomic layer deposition (ALD) is a technique that is highly scalable and widely used in CMOS manufacturing.…”

In-situ characterization of Ga2O passivation of In0.53Ga0.47As prior to high-k dielectric atomic layer deposition

“…5 and 6) and Ge (Ref. 7) interfacial passivation layers (IPLs) and Gd containing gadolinium gallium oxide (GGO) interfacial oxides [8][9][10] have been employed in an attempt to control the chemical species present at the interface. Previous work has indicated the presence of Ga 2 O at the interface of devices showing improved capacitance-voltage (CV) and drain current-gate voltage (I d -V g ) characteristics on GaAs(100).…”

A combined capacitance-voltage and hard x-ray photoelectron spectroscopy characterisation of metal/Al2O3/In0.53Ga0.47As capacitor structures

“…The inability to move the n-InGaAs Fermi level to the lower bandgap and the slight Fermi level movement of only 0.03 eV towards VBM for the p-InGaAs suggest a peak D it distribution where the density increases in the lower half of the bandgap, consistent with previous publications. [26][27][28] Fermi level alignment between the metal and the InGaAs is achieved by not only the movement of InGaAs Fermi level but also a change in the potential drop across the oxide layer. The change in the oxide potential following metal deposition will result in a binding energy shift of the associated Al 1s dielectric core levels, and the total potential drop across the oxide will result in an energy broadening of the peak.…”