Atomistic Simulation of Realistically Sized Nanodevices Using NEMO 3-D—Part I: Models and Benchmarks

Klimeck, Gerhard; Ahmed, Shaikh; Bae, Hagyoul; Kharche, Neerav; Clark, Steve; Haley, Benjamin P; Lee, Sunhee; Naumov, Maxim; Ryu, Hoon; Saied, Faisal; Prada, Marta; Korkusiński, Marek; Boykin, Timothy B.; Rahman, Rajib

doi:10.1109/ted.2007.902879

Cited by 223 publications

(188 citation statements)

References 37 publications

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“…To obtain the bandstructure of the NWs we use the nearest neighbor sp 3 d 5 s * tightbinding model [11,26,27,28,29], which captures all the necessary band features, and in addition, is robust enough to computationally handle larger NW cross sections as compared to ab-initio methods. As an indication, the unit cells of the NWs considered in this study contain up to ~5500 atoms.…”

Section: Approachmentioning

confidence: 99%

Bandstructure and mobility variations in p-type silicon nanowires under electrostatic gate field

Neophytou

Baumgärtner

Stanojević

et al. 2013

Solid-State Electronics

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The sp 3 d 5 s * -spin-orbit-coupled atomistic tight-binding (TB) model is used for the electronic structure calculation of Si nanowires (NWs), self consistently coupled to a 2D Poisson equation, solved in the cross section of the NW. Upon convergence, the linearized Boltzmann transport theory is employed for the mobility calculation, including carrier scattering by phonons and surface roughness. As the channel is driven into inversion, for [111] and [110] NW devices of diameters D>10nm the curvature of the bandstructure increases and the hole effective mass becomes lighter, resulting in a ~50% mobility increase. Such improvement is large enough to compensate for the detrimental effect of surface roughness scattering. The effect is very similar to the bandstructure variations and mobility improvement observed under geometric confinement, however, in this case confinement is caused by electrostatic gating. We provide explanations for this behavior based on features of the heavy-hole band. This effect could be exploited in the design of p-type NW devices. We note, finally, that the "apparent" mobility of low dimensional short channel transistors is always lower than the intrinsic channel diffusive mobility due to the detrimental influence of the so called "ballistic" mobility.

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Section: Approachmentioning

confidence: 99%

Bandstructure and mobility variations in p-type silicon nanowires under electrostatic gate field

Neophytou

Baumgärtner

Stanojević

et al. 2013

Solid-State Electronics

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“…Another simplification is to leverage the locality of interactions by ignoring integrals between wellseparated orbitals. Tight-binding (TB) [36,37] and densityfunctional tight binding (DFTB) [38] methods that make use of these approximations are computationally attractive alternatives for electronic structure modeling of silicon donor qubit devices. Whereas TB methods have been used extensively for modeling silicon donor systems [31,32,[39][40][41][42][43], DFTB methods have not yet been extensively applied.…”

Section: Donor Electron Wave Function Simulationsmentioning

confidence: 99%

“…However, for larger diameters, the computational costs of DFT were too demanding. In this case, we found that the semi-empirical TB models implemented within the NanoElectronic Modeling in three-dimensions (NEMO 3D) code were capable of addressing these larger sized particles [36,37]. Using NEMO-3D, the nanocrystals were modeled by a cubic box with a zinc blende lattice of Si and a cube length of a in the range of 1-30nm.…”

Section: Donor Electron Wave Function Simulationsmentioning

confidence: 99%

A computational workflow for designing silicon donor qubits

et al. 2016

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Developing devices that can reliably and accurately demonstrate the principles of superposition and entanglement is an on-going challenge for the quantum computing community. Modeling and simulation offer attractive means of testing early device designs and establishing expectations for operational performance. However, the complex integrated material systems required by quantum device designs are not captured by any single existing computational modeling method. We examine the development and analysis of a multi-staged computational workflow that can be used to design and characterize silicon donor qubit systems with modeling and simulation. Our approach integrates quantum chemistry calculations with electrostatic field solvers to perform detailed simulations of a phosphorus dopant in silicon. We show how atomistic details can be synthesized into an operational model for the logical gates that define quantum computation in this particular technology. The resulting computational workflow realizes a design tool for silicon donor qubits that can help verify and validate current and nearterm experimental devices.

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“…Before simulating the HEMTs, we extract the channel effective masses of the III-V HEMT devices from atomistic sp 3 d 5 s* tight-binding simulations using the NEMO-3D program [28]. The bandstructure calculated with the atomistic tight-binding model incorporates the non-parabolicity effects as well as the strain effects due to the lattice mismatch between the In 0.53 Ga 0.47 As/In 0.7 Ga 0.3 As layers.…”

Section: Materials Parametersmentioning

confidence: 99%

Device Physics and Performance Potential of III-V Field-Effect Transistors

Liu

Pal²,

Lundstrom³

et al. 2010

Fundamentals of III-V Semiconductor MOSFETs

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The device physics and technology issues for III-V transistors are examined from a simulation perspective. To examine device physics, an InGaAs HEMT structure similar to those being explored experimentally is analyzed. The physics of this device is explored using detailed, quantum mechanical simulations based on the non-equilibrium Green's function formalism. In this chapter, we: (1) elucidate the essential physics of III-V HEMTs, (2) identify key technology challenges that need to be addressed, and (3) estimate the expected performance advantage for III-V transistors. IntroductionDriven by tremendous advances in lithography, the semiconductor industry has followed Moore's law by shrinking transistor dimensions continuously for the last 40 years. The big challenge going forward is that continued scaling of planar, silicon, CMOS transistors will be more and more difficult because of both fundamental limitations and practical considerations as the transistor dimensions approach ten nanometers. The issues at small gate lengths are many fold. First, transistor scaling increases the number of gates on a chip and the operating frequency. To prevent the chip from overheating, the power dissipation should be limited, which requires lowering the power supply voltage while maintaining the ability to deliver high oncurrents for each new generation of technology. Secondly, the drain bias decreases the energy barrier height between the source and channel in a transistor due to 2D electrostatics. Degraded short channel effects become more significant as the gate length gets shorter, and the increased off-state leakage has pushed the standby power to its practical limit. Thirdly, the accompanying scaled oxide thickness provides better gate control of the channel potential, but this inevitably increases S. Oktyabrsky, P. D. Ye (eds.), Fundamentals of III-V Semiconductor MOSFETs,

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Atomistic Simulation of Realistically Sized Nanodevices Using NEMO 3-D—Part I: Models and Benchmarks

Cited by 223 publications

References 37 publications

Bandstructure and mobility variations in p-type silicon nanowires under electrostatic gate field

Bandstructure and mobility variations in p-type silicon nanowires under electrostatic gate field

A computational workflow for designing silicon donor qubits

Device Physics and Performance Potential of III-V Field-Effect Transistors

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