Atomic Layer-deposited Si-nitride/SiO/sub 2/ stack gate dielectrics for future high-speed DRAM with enhanced reliability

Abstract

Atomic layer-deposited (ALD) Si-nitride/SiO 2 stack gate dielectrics were applied to high-performance transistors for future scaled DRAMs. The stack gate dielectrics of the peripheral pMOS transistors excellently suppress boron penetration. ALD stack gate dielectrics exhibit only slightly worse negative-bias temperature instability (NBTI) characteristics than pure gate oxide. Enhanced reliability in NBTI was achieved compared with that of plasma-nitrided gate SiO 2. Memory-cell (MC) nMOS transistors with ALD stack gate dielectrics show slightly smaller junction leakage than those with plasma-nitrided gate SiO 2 in a high-drain-voltage region, and have identical junction leakage characteristics to transistors with pure gate oxide. MCs having transistors with ALD stack gate dielectrics and those with pure gate oxide have the identical retention-time distribution. Taking the identical hole mobility for the transistors with ALD stack gate dielectrics to that for the transistors with pure gate oxide both before and after hot carrier injection (previously reported) into account, the ALD stack dielectrics are a promising candidate for the gate dielectrics of future high-speed, reliable DRAMs.

Mechanism of Dynamic Bias Temperature Instability in p- and nMOSFETs: The Effect of Pulse Waveform

“…The flat-band voltages (V fb ) extracted from the high-frequency capacitance-voltage measurement for these three wafers are 1.10, 1.02, and 0.98 V for p-type gate and −1.02, −1.01, and −1.00 V for n-type gate, respectively. The difference in V fb of the p-type gate samples arises from the boron penetration, as the SiON film with higher nitrogen content can suppress the boron penetration more effectively [21]. On the other hand, the similarity in V fb of the n-type gate samples indicates that the nitridation-related positive trapped charge in the bulk oxide is minor or has similar density for our three wafers with different nitrogen contents.…”

Improvement in Mobility and Negative-Bias Temperature Instability in Metal–Oxide–Semiconductor Field-Effect Transistors with Atomic-Layer-Deposited Si–Nitride/SiO2 Stack Dielectrics

“…1 in ref. 5). To further clarify the reason of the V th difference, the V th values of the n þ -and p þ -poly-Si-gated n-and p-MOSFETs in other lot (all the samples have an expected EOT of 2.5 nm) are compared in Fig.…”

“…The atomic-layerdeposition (ALD) of Si nitride on SiO 2 can provide such a nitrogen distribution. It has been demonstrated that MOSFETs with ALD Si-nitride/SiO 2 stack gate dielectrics exhibit excellent boron suppression 5) and superior reliability characteristics 6) as compared with their counterparts with pure-SiO 2 or plasma-nitrided SiON gate dielectrics. To implement the Si-nitride/SiO 2 stack dielectrics in the next MOSFET technology generation, the effect of the stack gate dielectrics on carrier mobility should be clarified.…”

Influence of bulk bias on negative bias temperature instability of p-channel metal-oxide-semiconductor field-effect transistors with ultrathin SiON gate dielectrics

“…The negative bias temperature instability ͑NBTI͒ of p-channel metal-oxide-semiconductor field-effect transistors ͑pMOSFETs͒ has become an important reliability concern in modern complementary metal-oxide-semiconductor ͑CMOS͒ technology, especially when the gate-oxide thickness is scaled down to less than 2.0 nm and also nitrogen is introduced into the gate-SiO 2 film in order to suppress the boron penetration and to increase the dielectric constant. 1,2 Considerable efforts have been done for both static ͑Refs. 3-6͒ and dynamic ͑Refs.…”