Atmospheric plasma-enhanced spatial-ALD of InZnO for high mobility thin film transistors

Abstract

In this manuscript, the authors investigate the growth of indium zinc oxide, indium zinc oxide (InZnO, IZO) as a channel material for thin-film transistors. IZO is grown at atmospheric pressure and a high deposition rate using spatial atomic layer deposition (S-ALD). By varying the ratio of diethylzinc and trimethylindium vapor, the In/(In + Zn) ratio of the film can be accurately tuned in the entire range from zinc oxide to indium oxide. Thin film transistors with an In to Zn ratio of 2:1 show high field-effect mobility—exceeding 30 cm2/V s—and excellent stability. The authors demonstrate large scale integration in the form of 19-stage ring oscillators operating at 110 kHz. These electrical characteristics, in combination with the intrinsic advantages of atomic layer deposition, demonstrate the great potential of S-ALD for future display production.

Large‐area spatial atomic layer deposition of amorphous oxide semiconductors at atmospheric pressure

“…The measured bias stress is significantly lower than for SA IGZO TFTs on glass realized at Holst Centre using sputtered IGZO, ie, PGBS of approximately 1 V and NGBS greater than 5 V. We have previously already shown bias stress less than 250 mV for sALD IZO ESL TFTs. We attribute the increased TFT stability, both in ESL and SA architectures, to the absence of high‐energy species during the sALD deposition process, preventing the formation of lattice defects in the semiconductor layer or at the interfaces between the semiconductor and the dielectric layers . ALD‐deposited dielectric layers have actually been shown to improve bias stress stability by passivating such electron trap states, acting simultaneously as water permeation barriers …”

“…The three metal precursors were premixed and then fed into the sALD reactor zone. In previous work, we have shown that the In:Zn ratio in InZnO films, deposited by sALD, could be precisely controlled by changing the partial pressure of TMI and DEZ. Co‐injecting these precursors yielded amorphous InZnO films with uniform composition and low‐carbon content.…”

“…We attribute the increased TFT stability, both in ESL and SA architectures, to the absence of high-energy species during the sALD deposition process, preventing the formation of lattice defects in the semiconductor layer or at the interfaces between the semiconductor and the dielectric layers. 6 ALD-deposited dielectric layers have actually been shown to improve bias stress stability by passivating such electron trap states, acting simultaneously as water permeation barriers. 14,15 We note that in our top-gated SA TFTs, a lowtemperature PECVD SiO 2 gate dielectric is deposited on top of the sALD semiconductor layer, while the hydrogen doping of the semiconductor at the contact regions is mainly determined during the SiN intermetal dielectric deposition.…”

“…In this way, the need for time‐consuming purge steps is eliminated . Previously, we demonstrated TFTs with spatial atomic layer deposition (sALD) IZO deposited in an annular shape on a 6‐inch wafer …”

“…5 Previously, we demonstrated TFTs with spatial atomic layer deposition (sALD) IZO deposited in an annular shape on a 6-inch wafer. 6 In this work, our sALD process was scaled to largersize glass substrates (32 × 35 cm 2 ) using a home-built deposition tool. We use plasma-enhanced sALD to deposit the industry standard IGZO.…”