ATM shared-memory switching architectures

García-Haro, Joan; Jajszczyk, Andrzej

doi:10.1109/65.298160

Cited by 57 publications

(7 citation statements)

References 26 publications

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“…From previous studies it is well known that the shared buffer ATM switch architecture has the best performance in terms of throughput and cell loss probability. 1 Many analytical models have been developed in the literature for a shared buffer switch † because of its practical interest. One of the most common approaches in modelling a shared buffer switch is the vectorial model.…”

Section: Introductionmentioning

confidence: 99%

Performance analysis of shared buffer ATM switches with different cell departure models

Fong¹,

Singh²

1998

Int. J. Commun. Syst.

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Performance analysis of an asynchronous transfer mode (ATM) switch involves modelling the input traffic source, the switching mechanism and the cell departure process. An important issue, which determines the overall accuracy in performance evaluation of the switch, is the use of an appropriate probabilistic model to describe the cell departure process. Until now, little work has been done in the literature on comparing models of the cell departure process for studying the performance of an ATM switch. This paper compares and assesses the accuracy of several models, including a new one proposed by us, called the 'urn model'. These models are put under test in a performance evaluation of a shared buffer ATM switch, by using a discrete-time Markov chain. The numerical results are compared with the simulation and show that the urn model is a good compromise between accuracy and efficiency. This finding is significant because it helps to speed up convergence of an analytical model of a large network while providing satisfactory accuracy. † This is referred to as a shared memory-type non-blocking switch, with all input and output ports being able to access a shared memory module (or shared buffer) at a maximum speed of reading or writing b cells in a clock cycle.

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Section: Introductionmentioning

confidence: 99%

Performance analysis of shared buffer ATM switches with different cell departure models

Fong¹,

Singh²

1998

Int. J. Commun. Syst.

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“…Most of the shared memory switches provide one logical queue per port. The queue, called an address queue [5], consists of the cell-stored memory addresses. The available buffer spaces are stored in the idle address pool.…”

Section: Previously Proposed Switchesmentioning

confidence: 99%

“…A place in the queue is the memory address which refers to the cell stored space. This logical queue is called an address queue [5]. Previously proposed switches can be categorized into the following three types.…”

Section: Introductionmentioning

confidence: 99%

A shared-memory ATM switch with multicast function

Okoge

Ishiguro

Yamakita

1999

Electron. Comm. Jpn. Pt. I

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“…Recently, shared-buffer ATM switches have been proposed [1]. They can improve utilization of the buffer memory and then provide low loss rate.…”

Section: Introductionmentioning

confidence: 99%

An approximate transient analysis of dynamic thresholds in an ATM switch with shared buffer memory

Zouta

Ishiguro

Yamakita

2001

Electron. Comm. Jpn. Pt. I

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To achieve a fair share of buffer memory among the output queues in a shared buffer ATM switch, a maximum allowable queue length (a threshold) for each queue should be set. In this paper, to analyze a transient behavior of the buffer state in such switches, we perform a discrete‐time transient analysis of a queuing model and then approximately derive time‐varying queue length distribution and cell loss probability. In numerical examples, we discuss the validity of our analytical approach by comparison with simulation results. © 2001 Scripta Technica, Electron Comm Jpn Pt 1, 84(6): 1–10, 2001

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ATM shared-memory switching architectures

Cited by 57 publications

References 26 publications

Performance analysis of shared buffer ATM switches with different cell departure models

Performance analysis of shared buffer ATM switches with different cell departure models

A shared-memory ATM switch with multicast function

An approximate transient analysis of dynamic thresholds in an ATM switch with shared buffer memory

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